Signal Processing for Aperture Arrays

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Presentation transcript:

Signal Processing for Aperture Arrays

256 antenna elements distributed over AAVS1 Assumption: 256 antenna elements distributed over 4 stations 64 elements each

AAVS1 Setup 64 elements Station 1 Station 2 Station 3 Station 4 Correlator

Station architecture Receiver board Digital processing board X pol. Antennas Y pol. Antennas Architecture: ADCs centrally

UniBoard Related Hardware ADU UniBoard Presented December 2011

Current Status

Hardware Numbers ADU UniBoard 400-800 MHz (can be modified) Dual ADC with fmax=1 GHz 8 bit UniBoard 16 signal paths Input bandwidth: 400 MHz Output bandwidth: 40 beams of 300 MHz

Required changes for AAVS1 ADU filter removed Sampling @ 1 GHz UniBoard input bandwidth 1 GHz

How much hardware required? Per AAVS1 station: 2*64/16 = 8 UniBoards (2 represents X and Y pol.) Total: 32 UniBoards required

UniBoard Cost Breakdown

UniBoard2 Seeking for applications My (ASTRON hat) take: AAVS2 towards SKA1 will be the main application

SKA1 Station Number of elements: 11,264 Input bandwidth per element: 500 MHz Total output bandwith: 1 Tbps Two-stage beamforming First stage options: Integrated with ADC near antennas Analog/digital beamforming Centrally Second stage option: Implemented centrally for 11,264.y/x with x amount of combined elements in first stage and y amount of independent beams formed

Number of required boards Total input data rate: 2*11,264*8 bit * 1 G = 360 Tbps Current amount of 8 bit receiver inputs: 16 UniBoard2 (assumed): 64 Required max. UniBoard2 resources*): 2*176 boards (assumes 8 FPGAs/board) *) If input bandwidth is the bottle neck

Signal processing design And dependent on how smart we design, we will need less in the end This is an upper bound (disclaimer if bandwidth is the bottle neck) Example if we have a chip wherein 16 ADCs are combined and a first stage digital beamformer we need 16x boards less

UniBoard2 Initial Ideas FPGA technology: 20 nm Focused on power reduction Component selection Production (lead free now) Components switched off when not used etc. Interfaces: 2x4x25G per FPGA (QSFP+) ≥ 8 FPGAs Backplane oriented (to built larger, dense systems) ≥ 4 times more processing ≥ 4 more receiver input bandwidth Prototype available in 2014 SKA could and should drive the design decisions …