In an interrupt I/O system, deadlines put restriction on how long interrupts may remain disable. The deadline establish a priority among interrupt requests. Devices with shorter deadlines should be acknowledged first. Daisy-chained acknowledge signal partially solves the problem.

Review

CS501 Advanced Computer Architecture Lecture30 Dr.Noor Muhammad Sheikh

The solution is to allow high-priority devices to interrupt lower- priority handlers. It is necessary that interrupts should be enabled at some time during interrupt handler execution. Nested interrupts allow an interrupt handler to be interrupted.

Interrupts must remain disable during critical sections.

Critical section is a code sequence in the dandler during which a second interrupt would interfere. In SRC, interrupts must be remain disabled until the IPC and II registers are saved. Also, the devices with lower-priority, are disabled before enabling interrupts.

Steps in the Response of a Nested Interrupt Handler: Save the state changed by interrupt (IPC and II); (2) Disable lower priority interrupts; (3) Reenable exception processing; (4) Service interrupting device;

(5) Disable exception processing; (6) Reenable lower priority interrupts; (7) Restore saved interrupt state (IPC and II); (8) Return to interrupted program and reenable exceptions.

(2) Disable lower priority interrupts (6) Reenable lower priority interrupts;

Interrupt Masks for Executing Device j Handler A priority interrupt scheme could be managed using device-enable bits. Order the bits from left to right in order of increasing priority to form an interrupt mask.

Value of the mask when executing device j interrupt handler is: y h i g h p r i o r i t y 1 1 1 1 1 d e v i c e j e n a b l e

The priority mask should be distinct from individual enables. The value of a mask of the preceding priority form is determined by the interrupt-level j of the current handler. The interrupt-level mask should be different from a simple collection of enable bits.

For the devices of same priority: A daisy-chained acknowledge is needed to arbitrate simultaneous requests. Order of devices on the chain is not important within the group.

Priority Interrupt System with m = 2k Levels q l o a d k A B C m p t < c 1 – D P i y n u v

Priority Interrupt Mechanism is a separate subsystem. Many Commercial processors have a priority mechanism built into their exception response. Example: Motorola MC68000

Problem statement:1 Assume that three I/O devices are connected to a 32-bit, 10 MIPS CPU.The first device is a hard drive with a maximum transfer rate of 1MB/sec using a 32-bit bus. The second device is a floppy drive with a transfer rate of 25KB/sec over a 16-bit bus, and the third device is a keyboard that must be polled thirty times per second. Assuming that the polling operation takes 20 instructions for each I/O device, determine the percentage of CPU time required to poll each device.

Solution for Hard Disk For hard drive Data transfer rate =1MB/sec =250 K 32-bit words every second. Using 1K=210 , the number of CPU = 250 * 210 *20 instructions required = 5120000=5.12 MIPS % of CPU time = (5.12 * 106)/ (10 *106) required for polling =51.2%

Solution for floppy drive: For floppy disk : Data transfer rate =25K/2 = 12.5* 210 half-words/sec. Number of CPU = 12.5 * 210 * 20 instructions = 256000 required The % of CPU time = ( 0.256 * 106)/ ( 10 * 106) required for polling = 2.56%

Solution for Key board: For the keyboard The number of instructions = 30 * 20 required for polling = 600 inst./sec Therefore, % of CPU time = 600 / (10 * 106) spent in polling =0.006%

Problem statement:2 a): What should be the polling frequency for an I/O device if the average delay between when the device wants to make a request and the time it is polled to be at most 10 ms? b): If it takes 10,000 cycles to poll the I/O device, and the processor operates at 100MHz, what % of the CPU time is spent polling? c): What if the system wants to provide an average delay of 1 ms?

Solution a: Assume: The I/O requests are distributed evenly in time. The average time that a device will have to wait for the processor to poll is half the time between polling attempts. Therefore, to provide an average delay of 10 ms, the processor will have to poll every 20 ms, or 50 times per second.

Solution b If each polling attempt takes 10,000 cycles, then the processor will spend 500,000 cycles polling each second. % of CPU time = (0.5*106)/(100*106) spent polling =0.5%

Continued It is acceptable to use polling for a key board and floppy drive, but not for a hard disk. For devices with higher data rates, the use of polling is not suggested.

Solution c To provide an average delay of 1ms, the polling frequency must be increased. The processor will have to poll every 2ms, or 500 times per second. This will consume 5,000,000 cycles for polling. % of CPU time = 5/100 =5%. for polling

Problem statement:3 What percentage of time will a 20MIPS processor spend in the busy wait loop of an 80-character line printer when it takes 1 ms to print a character and a total of 565 instructions need to be executed to print an 80 character line. Assume that two instructions are executed in the polling loop.

Solution Out of the total 565 instructions executed to print a line, 80*2=160 are required for polling. For a 20MIPS processor: The execution time for the remaining 405 instructions = 405/(20*106) = 20.25sec. Since the printing of 80 characters takes 80ms, (80-0.02025)=79.97 ms is spent in the polling loop before the next 80 characters can be printed. This is 79.97/80=99.96% of the total time.

Problem statement:4 Consider a 20 MIPS processor with several input devices attached to it each running at 1000 characters per second. Assume that it takes 17 instructions to handle an interrupt. If the hardware interrupt response takes 1sec, what is the maximum number of devices that can be handled simultaneously?

Solution Time for service of one character 17/(20*106)+1sec=1.85sec. 1.85 ms of handling time is required by each device every second. Therefore the maximum number of devices that can be handled =1/(1.85*10-3)= 540.

Problem statement:5 Assume that a floppy drive having a transfer rate of 25KB per second is attached to a 32 bit, 10MIPS CPU using an interrupt driven interface. The drive has a 16-bit data bus. Assume that the interrupt overhead is 20 instructions. Calculate the fraction of CPU time required to service this drive when it is active.

Solution As the floppy drive has a 16-bit data bus, it can transfer two bytes at one time. Transfer rate = 25/2 = 12.5K half-words/ second. overhead of 20 instructions=12.5K * 20 = 12.5 *210 * 20 = 256000 inst./sec. This is 2.56% of the CPU time.

Problem Statement:6 A processor with 500 MHz clock requires 1000 cycles to perform a context switch and start an interrupt handler. Assume each interrupt takes 10000 cycles to handle and the device makes 200 requests per second Also assume that the processor polls every 0.5ms if not using interrupts and polling an I/O device require 500 cycles. Compute the following. a): How many cycles per second does the processor spend handling I/O from the device if interrupts are used? b): How much of the processor time is used in interrupt handling if the I/O device makes 200 requests per second? c): How many cycles per second are spent on I/O if polling is used? Do not include any context switch time. d): How often the processor should poll for polling to take as many cycles per second as interrupts?

Solution a) Number of cycles taken by each interrupt =10,000+2000=12,000 cycles. A total of 200*12,000=2,400,000 cycles are spent handling interrupts every second. b) % of processor time =2,400,000/(500x106) or 0.48%.

The interrupt overhead = 1000 cycles/sec for a context switch to the interrupt service routine and 1000 cycles/sec back from it. This means a total of 2000 cycles/sec with 200 interrupts/sec this amounts to 400,000 cycles/sec. The polling overhead is 500cycles/sec. Thus for the same overhead as interrupts ,the polling operation should be performed with 400,000/500=800 polls/sec or 1.25msec.

d) Each polling attempt takes 500 cycles, so the processor can do 400,000/500=800 polls/sec and spends the same fraction of its time handling I/O via polling as with interrupts.

ld [2], [9] Transfer data from memory location 9 to memory location 2 Illegal instruction

ld r1, [9] st r1, [2]

Out [6], dataport Illegal

ld r1, [6] out r1, dataport

CPU acts as an unnecessary middleman Every data word travels over the system bus twice

Higher transfer rate Additional DMA controller required

DMA requests have priority over interrupts

Summary