MV5: A RECONFIGURABLE SIMULATOR FOR HETEROGENEOUS MULTICORE ARCHITECTURES Jiayuan Meng*, Kevin Skadron University of Virginia * Now at Argonne National Laboratory Single-Instruction, Multiple-Threads Do you need it? Simulators for Today’s Architectures Break it, Use it! GPU-like SIMD (SIMT) Hardware thread scheduler API for SIMD threads Directory-based coherence (MESI, MSI) On-chip Network (Mesh) Simulation Management for space exploration M5 based So what is MV5? A B C D (b) Branch divergence and re-convergence time A / 11111111 B / 11111001 D / 11111111 C / 00000110 (a) The example program Post-dominator If you want to explore: SIMD + IO/OO SIMD + coherent caches SIMD + OCN Simple Banked Cache Underlying middleware If you are OK with System emulation Kernels Out-of-Order (OO) core: SimpleScalar Simultaneous Multithreading: SMTSIM Chip-multiprocessor w/t OO cores: SESC Chip-multiprocessor w/t In-Order (IO), OO cores: Simics+Gems+Garnet, SimFlex Intel’s Microarchitecture: PTLSim GPU: GPGPUSim But Future is Unpredictable… Core L1 Cache DRAM L2 Cache BlkState DirState Separate basic cache functionalities with coherence protocols General purpose / Heterogeneous / Integrated Accelerators? Diversity Modularity Scalability Co-design M5 provides such a platform MV5 is based on M5 Potential Configurations MESI/MSI Dual Core Tiled Cores OO+SIMD Note: SIMD cores can share the same address space with other cores over coherent caches! OO SIMD On-chip Network In-order MV5 Website https://sites.google.com/site/mv5sim/home MV5 Mailing list: http://groups.google.com/group/mv5sim caches DRAM Acknowledgements This work was supported in part by SRC grant No. 1607, NSF grant nos. IIS-0612049 and CNS-0615277, a grant from Intel Research, and a professor partnership award from NVIDIA Research. We would like to thank Jeremy W. Sheaffer, David Tarjan, Shuai Che, and Jiawei Huang for their helpful inputs in power modeling, area estimation, and benchmark implementations.