Layout and fabrication of CMOS circuits

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Presentation transcript:

Layout and fabrication of CMOS circuits This week Layout and fabrication of CMOS circuits After an idea from Peter.Nilsson@es.lth.se

Fabrication of CMOS circuits A short introductory review CMOS technology Fabrication of CMOS circuits A short introductory review After an idea from Peter.Nilsson@es.lth.se

Photolithography Deposit a layer Spin-on photoresist Use mask to pattern layer Expose photoresist Develop photo-resist Leaves only un-exposed resist Etch pattern Silicon substrate Remove photo resist (ashing)

CMOS Layout Well-mask Active-mask Shallow trench Isolation (STI) in Well-mask Active-mask Shallow trench Isolation (STI) out out in VSS VDD poly-mask N+-select-mask N+-diffusion P+-select-mask P+-diffusion Body-ties Field oxide Contact-mask p-type silicon substrate p+ n+ n-well VDD-contact Contact-etch VSS-contact Metal-mask MCC091 – Introduction to Integrated Circuit Design

Bowl, c. 1292-1341 Syrian-Egyptian Brass with silver and copper inlay Damascene technology Damascening technique A pattern is cut into the substrate metal The inlay (gold) metal is hammered into the carved areas Process is complete, with metal decorations inlaid into the metal A pattern is etched into the silicon substrate Copper is applied to completely cover the substrate The applied metal is planarized by chemical/ mechanical polishing (CMP) to expose wires Damascening a computer chip Bowl, c. 1292-1341 Syrian-Egyptian Brass with silver and copper inlay

Copper Damascene Tungsten via plugs Single and dual damascene Intra- & inter- metal insulator Metal 2 trenches Metal 2 electroplating CMP Insulator Via etch p-substrate p+ n+ Metal3 trench etch VDD-contact VSS-contact n-well Metal3 Cu CMP MCC091 – Introduction to Integrated Circuit Design