Sequential Logic

Sequential Logic Circuits So far we have only considered circuits where the output is purely a function of the inputs With sequential circuits the output is a function of the values of past and present inputs Examples of sequential circuits A counter to count the number of times a signal has changed A traffic light controller (remembering where it is up to in the sequence) X = X + A 2

Sequential circuit concepts The addition of a memory device to a combinational circuit allows the output to be fed back into the input: circuit Input(s) Output(s) memory

Synchronous and Asynchronous circuit Input(s) Output(s) memory Clock pulse With synchronous circuits a clock pulse is used to regulate the feedback, input signal only enabled when clock pulse is high – acts like a “gate” being opened.

Flip Flop A bi-stable element. Two stable states, 1 or 0. Able to store a digital value. Depends on the input and the previous value stored. Basic elements of a memory device in a digital computer. The outputs of Q and Q’ are complemented to each other. 6

The SR Flip-Flop Consider the following circuit R R R Q Q Q S S Q Q S Symbol Circuit R S Qn+1 0 0 Qn 0 1 1 1 0 0 1 1 ? n+1 represents output at some future time n represents current output. Function Table Although SR LAtch is one of the most important fundamental methods of didgital storage,it is not often used in practice (because of undefined state) - However forms the basis of the more complex latches that we will be dicussing 7

SR operation Assume some previous operation has Q as a 1 Assume R and S are initially inactive Indicates a stable state at some future time (n+ = now plus) R = 0 Q = 1 R S Qn+1 0 0 Qn 0 1 1 1 0 0 1 1 ? ~Q = Q, ie is the complement of Q. S = 0 Q = 0 Circuit

Reset goes active R = 1 When R goes active 1, the output from the first gate must be 0. Q = 0 This 0 feeds back to gate 2 S = 0 ~Q = 1 Since both inputs are 0 the output is forced to 1 The output ~Q is fed back to gate 1, both inputs being 1 the output Q stays at 0. R = 1 Q = 0 S = 0 ~Q = 1

Application of the SR Latch An important application of SR latches is for recording short lived events e.g. pressing an alarm bell in a hospital 12

D Flip-Flop It removes the undefined behaviour of the SR latch Often used as a basic memory element for the short term storage of a binary digit applied to its input Symbols are often labeled data and enable/clock (D and C) D D C Q S Q Q D C Qn+1 X 0 Qn Hold 0 1 0 Reset 1 1 1 Set C C R Q Q Circuit Symbol Function Table

Clocking Event What if the output only changed on a C transition? Q Q’ 0 0 1 1 1 0 X 0 Q0 Q0’ D C Q Q’ Positive edge triggered Lo-Hi edge Hi-Lo edge

D Flip-Flop Stores a value on the positive edge of C Input changes at other times have no effect on output C D Q Q’ 0 0 1 1 1 0 X 0 Q0 Q0’ D C Q Q’ Positive edge triggered D gets latched to Q on the rising edge of the clock.

Clocked D Flip-Flop Stores a value on the positive edge of C Input changes at other times have no effect on output

Positive and Negative Edge D Flip-Flop D flops can be triggered on positive or negative edge Bubble before Clock (C) input indicates negative edge trigger Lo-Hi edge Hi-Lo edge

JK Flip-flop The most versatile of the flip-flops Q The most versatile of the flip-flops Has two data inputs (J and K) Do not have an undefined state like SR flip-flops When J & K both equal 1 the output toggles on the active clock edge Most JK flip-flops based on the edge-triggered principle +ve edge triggered JK flip-flop The C column indicates +ve edge triggering (usually omitted) Talk about symbols for +ve and -ve edge-triggered flip flops Master-slave version susceptible J K C Qn+1 0 0 ­ Qn Hold 0 1 ­ 0 Reset 1 0 ­ 1 Set 1 1 ­ Qn Toggle X X X Qn Hold 29

J-K Flip Flop Logic Symbol Truth Table Input Output INPUTS OUTPUTS Data Complementary Normal Input Output Clock J K Q FF CLK Truth Table Mode of Operation INPUTS OUTPUTS Effect Input CLK J K Output Q Hold No Change Reset 1 Reset or cleared to 0 Set Set to 1 Toggle Changed to Opposite State

Clocked J-K Flip Flop Two data inputs, J and K J -> set, K -> reset, if J=K=1 then toggle output Characteristic Table

Two JK Flip-Flop, 1st is Master and 2nd is slave. Master Flip-Flop is positive edge triggered. Slave Flip-Flop is negative edge triggered. Slave follows master output. The output is delayed.

Master slave JK Flip-Flop

T Flip-Flop T (Toggle) flip-flop is a complementing one. T flip-flop is obtained from a JK when inputs J and K are tied together.

T Flip-Flop If T=0 ( J=K=0) output does not change. If T=1 ( J=K=1) output is complemented. A T flip-flop can also be made of D flip-flop and a XOR. D = T XOR Q = TQ’ + T’Q

Characteristic Table of T Flip-flop Q(t+1) Q(t) No change 1 Q’(t) Complement

Summary Flip flops are circuits controlled by a clock. Triggered on the edge of the pulse to avoid races with both inputs at 1 during the clock pulse. Because modern IC’s have a small propagation delay races can still occur. The master-slave configuration solves this problem by having only master or slave active at any one time.

Counters Counters are important components in computers The increment or decrement by one in response to input Two main types of counters Ripple (asynchronous) counters Synchronous counters Ripple counters Flip flop output serves as a source for triggering other flip flops All flip flops triggered by a clock signal Synchronous counters are more widely used in industry. credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20. Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.

Counters Binary counter Counter that follows a binary sequence N bit binary counter counts in binary from n to 2n-1 Ripple counters triggered by initial Count signal Applications: Watches Clocks Alarms Web browser refresh

Binary Ripple Counter Reset signal sets all outputs to 0 Count signal toggles output of low-order flip flop Low-order flip flop provides trigger for adjacent flip flop Not all flops change value simultaneously Lower-order flops change first

Asynchronous Ripple Counter

Asynchronous Counters Each FF output drives the CLK input of the next FF. FFs do not change states in exact synchronism with the applied clock pulses. There is delay between the responses of successive FFs. Ripple counter due to the way the FFs respond one after another in a kind of rippling effect.

Synchronous counters Synchronous(parallel) counters Remember All of the FFs are triggered simultaneously by the clock input pulses. All FFs change at same time Remember If J=K=0, flop maintains value If J=K=1, flop toggles Most counters are synchronous in computer systems. Can also be made from D flops Value increments on positive edge

Synchronous Counter FF0 is configured to change output state for every transition of the clock. FF1 changes output state when the output of FF0 is 1. When both Q0 and Q1 are at logical 1, the output FF2 changes state after the clock. FF3 changes state after the clock pulse when all other outputs are at logical 1. 56

Synchronous UP/Down counters Up/Down Counter can either count up or down on each clock cycle Up counter counts from 0000 to 1111 and then changes back to 0000 Down counter counts from 1111 to 0000 and then back to 1111 Counter counts up or down each clock cycle Output changes occur on clock rising edge

Registers

Overview Multiple flip flops can be combined to form a data register Shift registers allow data to be transported one bit at a time Registers also allow for parallel transfer Many bits transferred at the same time Shift registers can be used with adders to build arithmetic units Most digital hardware can be built from combinational logic (and, or, invert) and flip flops Basic components of most computers credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20. Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.

Basic data movement in shift registers A register is a digital circuit with two basic functions: Data Storage and Data Movement

Four bit Register Circuit Symbol D C Q D0 D1 D2 D3 Q0 Q1 Q2 Q3 clk D0 61

Shift Registers Points to note: At every clock pulse, the first flip flop is loaded with the value of the data in stream The data that was in this flip flop is then loaded into the second and so on. The data can be taken out of the last flip flop in serial form or it can be taken from all outputs at the same time – parallel form.

Shift Registers Shift registers can also be loaded using parallel input lines Therefore inputs can be parallel or serial Outputs can be parallel or serial Functions that shift registers can carry out include: Serial Loading Serial Output Parallel Output Parallel Loading This makes them suitable for a wide variety of tasks Serial loading - reading values off Da fill register in a serial fashion Serial Output - contents of register appear one by one on the Qd output as each clock pulse applied Parallel Output- Contents output in parallel using Qa through Qd Parallel loading - Contents of all registers loaded in a single clock pulse - Da through Dd available 65

Serial-In, Serial-Out A B D Q C CLR D Q C CLR D Q C CLR D Q C CLR RIN QD CK CLR_L

Serial-In, Parallel-Out D Q C CLR A D Q C CLR B D Q C CLR D Q C CLR RIN QA QB QC QD CK CLR_L