COP Interface Requirements JTAG/COP Header Required Optional 16 15 TDO - Test Data Output TDI - Test Data Input QACK - Quiescent Acknowledge TRST - Test Reset TCK - Test Clock TMS - Test Mode Select HRST - HRESET GND - Ground VDDS - VDD Sense SRST - SRESET CKSO - Checkstop Out CKSI - Checkstop In R/ST - Run/Stop 16 15 GND CKSO KEY 13 KEY HRST 12 11 NC SRST 10 9 NC TMS 8 7 CKSI TCK 6 5 VDDS R/ST QACK - Quiescent Acknowledge: Used for Host Processors only (MPC755, MPC7447, MPC7457, etc.) Must be asserted when debugging Host Processors Compare Freescale’s pinout to that from IBM RISCWatch Power Architecture Debug Connector: RISCWatch Connector Signal Names ----------------------------------------------- 1 TDO 2 unused 3 TDI 4 TRST 5 unused 6 POWER This is a status signal, not a power source. 7 TCK 8 unused 9 TMS 10 unused 11 SRESET/HALT (SRESET is not used by CodeWarrior) 12 unused 13 HRESET 14 KEY Pin in this location is removed. 15 CHECKSTOP 16 GND 4 3 TRST TDI 2 1 QACK TDO 2 1

HRESET and TRST Requirements TRST is required to be asserted during an HRESET assertion. IEEE 1149.1 requires that all components in TCK domain should be reset to their reset state only by going to Test-Logic-Reset state (TRST assertion).

HRESET and TRST Requirements COP debugger needs the ability to drive HRESET and TRST independently. • Support hot-plugging onto target system (TRST assertion without HRESET assertion). • Support resynchronizing with the system if the system is reset with on-board reset switch (TRST assertion without HRESET assertion) HRESET TRST COP halt During “COP Halt” sequence, the CodeWarrior debugger puts the processor into Soft Stop mode The Ethernet TAP/USB TAP uses COP commands to gain control of the target processor. COP commands are issued to the target processor through the JTAG lines. Therefore, the JTAG lines must be available to Ethernet TAP so it can issue its COP commands whenever required. Critical timing for Ethernet TAP/USB TAP is the trailing edge of the HRESET* signal. TRST* must be negated in time for Ethernet TAP/USB TAP to send several COP commands to the processor before HRESET* is negated. Processor control problems occur when the TRST* follows HRESET*. With TRST* asserted, the JTAG lines are held in reset. This means the JTAG lines cannot be used to send COP commands to the target processor. If the target processor does not receive the COP commands designed to stop when HRESET* is negated, the processor will begin executing target code instead. The Ethernet TAP/USB TAP generates the following TRST* and HRESET* signal timing when entering a debugger RESET command: 1) HRESET* asserts. 2) TRST* asserts about 100 milliseconds later. 3) TRST* negates about 100 milliseconds after assertion. 4) HRESET* negates about 100 milliseconds after TRST* negates. Clocking five “TMS = 1” cycles is equivalent to asserting TRST We do this in case one or more TRST pin is not connected on all processors TMS TCK 5 “TMS=1” Clocks

TARGET DESIGN - COP Interface Requirements Host PA JTAG Interface Connection This example from the Freescale “MPC7457 RISC Microprocessor Hardware Specifications” manual (MPC7457EC) Highlighted areas are important for use with Ethernet TAP, USB TAP HRESET and TRST must be independent of each other CodeWarrior tools have 100 Ohm pull-down on QACK Necessary only for processors that have a QACK input Diagram taken from Figure 26, http://www.freescale.com/files/32bit/doc/data_sheet/MPC7457EC.pdf This design allows for separate *HRESET and *TRST control from the COP header, but *HRESET asserted from the target (a Reset button for example) would assert both *HRESET and *TRST Notes: RUN/*STOP, normally found on pin 5 of the COP header, is not implemented on the MPC7457. Connect pin 5 of the COP header to OVdd with a 10-K ohm pull-up reisistor. Key location; pin 14 is not physically present on the COP header. Component not populated. Populate only if debug tool does not drive *QACK. Populate only if debug tool uses an open-drain type output and does not actively deassert *QACK. If the JTAG interface is implemented, connect *HRESET from the target source to *TRST from the COP header through an AND gate to *TRST of the part. If the JTAG interface is not implemented, connect *HRESET from the target source to *TRST of the part through a 0 ohm isolation resistor. Though defined as a No-Connect, it is a common and recommended practice to use pin 12 as an additional GND pin for improved signal integrity. Always consult the Hardware Specifications for your product

TARGET DESIGN - e300 JTAG Interface For CodeWarrior Tools: HRESET and TRST are independent from the COP header CHKSTP_OUT and CHKSTP_IN are not used by the CodeWarrior debugger SRESET is not used by the CodeWarrior debugger Diagram taken from Figure 43, http://www.freescale.com/files/32bit/doc/ref_manual/MPC8347EEC.pdf 1. The COP port and target board should be able to independently assert PORESET and TRST to the processor in order to fully control the processor as shown here. 2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection. 3. COP_RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the device. Connect pin 5 of the COP header to OVDD with a 10 kΩ pull-up resistor. Always consult the Hardware Specifications for your product

TARGET DESIGN – e500 JTAG Interface For CodeWarrior Tools: HRESET and TRST are independent from the COP header CHKSTP_OUT and CHKSTP_IN are not used by the CodeWarrior debugger SRESET is not used by the CodeWarrior debugger Diagram taken from Figure 60, http://www.freescale.com/files/32bit/doc/data_sheet/MPC8560EC.pdf 1. The COP port and target board should be able to independently assert HRESET and TRST to the processor in order to fully control the processor as shown here. 2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection. 3. The KEY location (pin 14) is not physically present on the COP header. 4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for improved signal integrity. 5. This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed. 6. Asserting SRESET causes a machine check interrupt to the e500 core. Always consult the Hardware Specifications for your product

TARGET DESIGN Target Checklist Before Starting PA Debugger Ensure HRESET not tied to TRST HRESET to the processor exclusive to COP/JTAG header Processor must be running properly Valid power Valid clocks Valid Reset Configuration TDI/TDO/TCK tied directly to processor* Multi-processor debugging introduced in 8.7 CodeWarrior Development Studio for Power Architecture HRESET exclusive to COP/JTAG header: problems arise when the core is reset and the debugger doesn’t know about it Usually the debugger will report the processor can not be put into STOP mode Processor must be running: COP/JTAG debugging requires the cooperation of the processor. This is a run-control tool, not an in-circuit emulator. Valid Reset Configuration applies mostly to PQ2 chips that fetch Reset Config Words from memory upon power-up. These RCW data must be valid, however they’re provided to the core - Two alternatives we’ll discuss later > Tie RSTCONF pin high > Feed RCW data from CodeWarrior debugger TDI, TDO, TCK routed through PLD, FPGA or other circuitry may adversely affect the JTAG/COP timing That said, some Freescale evaluation boards are designed with these signals routed through gate arrays