Data Center Networks and Fast and Programmable Switching Technologies

Slides:



Advertisements
Similar presentations
Programming Protocol-Independent Packet Processors
Advertisements

P4 demo: a basic L2/L3 switch in 170 LOC
How to tell your plumbing what to do Protocol Independent Forwarding
P4: specifying data planes
ENGINEERING WORKSHOP Compute Engineering Workshop P4: specifying data planes Mihai Budiu San Jose, March 11, 2015.
IP Forwarding Relates to Lab 3.
NetFPGA Project: 4-Port Layer 2/3 Switch Ankur Singla Gene Juknevicius
Forwarding Metamorphosis: Fast Programmable Match-Action Processing in Hardware for SDN Pat Bosshart, Glen Gibb, Hun-Seok Kim, George Varghese, Nick.
OpenFlow overview Joint Techs Baton Rouge. Classic Ethernet Originally a true broadcast medium Each end-system network interface card (NIC) received every.
OpenFlow Switch Specification-v part1 Speaker: Hsuan-Ling Weng Date: 2014/12/02.
400 Gb/s Programmable Packet Parsing on a Single FPGA Authors : Michael Attig 、 Gordon Brebner Publisher: 2011 Seventh ACM/IEEE Symposium on Architectures.
CS335 Networking & Network Administration Tuesday, April 20, 2010.
Data Center Virtualization: Open vSwitch Hakim Weatherspoon Assistant Professor, Dept of Computer Science CS 5413: High Performance Systems and Networking.
1 IP Forwarding Relates to Lab 3. Covers the principles of end-to-end datagram delivery in IP networks.
Software-Defined Networks Jennifer Rexford Princeton University.
Microsoft Windows Server 2003 TCP/IP Protocols and Services Technical Reference Slide: 1 Lesson 7 Internet Protocol (IP) Routing.
CS492b Project #3-2 KIP router KAIST Dept. of CS NC Lab.
Customizing OVS using P4 Muhammad Shahbaz with Sean Choi, Ben Pfaff, Chaitanya Kodeboyina, Changhoon Kim, Nick McKeown, Nick Feamster, and Jen Rexford.
P. Bosshart, D. Daly, G. Gibb, M. Izzard, N. McKeown, J. Rexford, C. Schlesinger, D. Talayco, A. Vahdat, G. Varghese, D. Walker SIGCOMM CCR, 2014 Presented.
Network Router Security Packeting Filtering. OSI Model 1.It is the most commonly refrenced protocol model. It provides common ground when describing any.
Forwarding Programming in Protocol- Oblivious Instruction Set Author : Jingzhou Yu, Xiaozhong Wang, Jian Song, Yuanming Zheng, Haoyu Song Conference: 2014.
VIRTUAL NETWORK PIPELINE PROCESSOR Design and Implementation Department of Communication System Engineering Presented by: Mark Yufit Rami Siadous.
PISCES: A Programmable, Protocol-Independent Software Switch
400 Gb/s Programmable Packet Parsing on a Single FPGA Author: Michael Attig 、 Gordon Brebner Publisher: ANCS 2011 Presenter: Chun-Sheng Hsueh Date: 2013/03/27.
Experiences with Programmable Dataplanes Ronald van der Pol SURFnet TNC 2016, June, Prague (CZ)
Nick McKeown (Many thanks to Lisa and Lavanya) CS244 Programmable Switches Forwarding metamorphosis: fast programmable match-action processing … Pat Bosshart,
BPF+ Exploiting Global Data-flow Optimization in a Packet Filter Architecture Andrew Begel, Steven McCanne, Susan L. Graham University of California, Berkeley.
P4: Programming Protocol-Independent Packet Processors
COS 561: Advanced Computer Networks
P4: specifying data planes
Scaling the Network Chapters 3-4 Part 2
Data Center Networks and Basic Switching Technologies
P4 (Programming Protocol-independent Packet Processors)
April 28, 2017 SUMIT MAHESHWARI INES UGALDE
IP Forwarding Covers the principles of end-to-end datagram delivery in IP networks.
Data Center Networks and Switching and Queueing
Reference Router on NetFPGA 1G
PISCES: A Programmable, Protocol-Independent Software Switch
Automated Parser Generation for High-Speed NIDS
Design of a Diversified Router: Packet Formats
Programmable Networks
The Stanford Clean Slate Program
2018/11/19 Source Routing with Protocol-oblivious Forwarding to Enable Efficient e-Health Data Transfer Author: Shengru Li, Daoyun Hu, Wenjian Fang and.
P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers
IP Forwarding Relates to Lab 3.
Network Core and QoS.
Dynamic Packet-filtering in High-speed Networks Using NetFPGAs
Network Fundamentals – Chapter 7
Design of a Diversified Router: November 2006 Demonstration Plans
Code Review for IPv4 Metarouter Header Format
Code Review for IPv4 Metarouter Header Format
Debugging P4 Programs with Vera
Network Fundamentals – Chapter 7
Reprogrammable packet processing pipeline
P4FPGA : A Rapid Prototyping Framework for P4
Network Fundamentals – Chapter 7
Network Fundamentals – Chapter 7
Network Fundamentals – Chapter 7
Network Layer: Control/data plane, addressing, routers
Programmable Switches
IP Forwarding Relates to Lab 3.
Ch 17 - Binding Protocol Addresses
A Simplified, Cost-Effective MPLS Labeling Architecture for Access Networks Harald Widiger1, Stephan Kubisch1, Daniel Duchow1, Thomas Bahls2, Dirk Timmermann1.
Networking and Network Protocols (Part2)
IP Forwarding Relates to Lab 3.
Reference Router on NetFPGA 1G
Packet Switch Architectures
Network Fundamentals – Chapter 7
Network Core and QoS.
Chapter 4: outline 4.1 Overview of Network layer data plane
Presentation transcript:

Data Center Networks and Fast and Programmable Switching Technologies Hakim Weatherspoon Assistant Professor, Dept of Computer Science CS 5413: High Performance Systems and Networking March 3, 2017 Slides used and adapted judiciously from Computer Networking, A Top-Down Approach

PISA: Protocol Independent Switch Architecture P4: Specifying packet processing logic Basic constructs: Header, Parser, Action, Table /* Header definition */ header_type ethernet_t { fields { dstAddr : 48; srcAddr : 48; etherType : 16; } } /* Parser */ parser parse_ethernet { extract(ethernet); return select(latest.etherType) { 0x800 : parse_ipv4; 0x806 : parse_arp; default : ingress; } } P4 is a dataplane programming language for packet processing. The best way to think about P4 is it is like the instruction set for packet processing pipeline, as a result, P4 provides a set of basic constructs to describe a packet processing pipeline, for example, you can define headers, parser, action and table in a packet pipeline. In this example, we define a ethernet header as a struct with three fields, dst, src and etherType; then we define a parser to extract information from the header and make a decision on the next parsing step. We designed an assembler for FPGA. Next, tables can be defined with two clauses. First the key that the table will match on. Second, the action to be performed on a packet if match is true. For example, we can define an action of drop, to drop a packet. An action can also take arguments, which is from an entry in the table. action _drop() { drop(); } action next_hop(arg1, arg2, …) { // instructions table forwarding_tbl { read { ipv4.dstAddr : lpm; } actions { next_hop; _drop; }}

PISA: Protocol Independent Switch Architecture P4: Specifying packet processing logic Basic constructs: Header, Parser, Action, Table /* Header definition */ header_type udp_t { fields { srcPort : 16; dstPort : 16; length : 16; checksum : 16; } } /* Parser */ header udp_t udp; parser parse_udp { extract(udp); return ingress; } } table table_count { read { udp.dstPort : exact; } actions { count_c1; _drop; }} P4 is a dataplane programming language for packet processing. The best way to think about P4 is it is like the instruction set for packet processing pipeline, as a result, P4 provides a set of basic constructs to describe a packet processing pipeline, for example, you can define headers, parser, action and table in a packet pipeline. In this example, we define a ethernet header as a struct with three fields, dst, src and etherType; then we define a parser to extract information from the header and make a decision on the next parsing step. We designed an assembler for FPGA. Next, tables can be defined with two clauses. First the key that the table will match on. Second, the action to be performed on a packet if match is true. For example, we can define an action of drop, to drop a packet. An action can also take arguments, which is from an entry in the table. action _drop() { drop(); } action count_c1(arg1, arg2, …) { // instructions control ingress { if { valid(eth)) { if { valid(ip4)) { if { valid(udp)) { apply (table_count); }}}}

PISA: Protocol Independent Switch Architecture

Before Next time Project Proposal HW2 due thoday Friday, March 3 Meet with groups, TA, and professor HW2 Chat Server Due this next Friday, March 10 Check website for updated schedule