LCLS Timing Software and Plan April 24 2012 Kukhee Kim ICD Software SLAC National Accelerator Laboratory

Contents Current configuration SLAC specific features On going issues Future plan and issues

Timing System Configuration 119 MHz clock + 360Hz Fiducial from RF timing system Timing Pattern from Master Pattern Generator (in old control system) 128 bits modifier ioc PNET VMTG EVG Fanout EVRs 360 Hz fiducial 6x32bits modifiers [0_255] event codes + BSA related information 476 MHz main drive line RF which carries the 360 Hz trigger modulation from Master Trigger Generator (new system)

Current Configuration Master Pattern Generator (in old control system) generates 128 bits timing pattern (+ beam code + pulse Id) at 360 Hz and broadcasts it on PNET PNET module in EVG IOC receives the timing information and drives the 360 Hz timing processing EVG software evaluates the timing pattern from the PNET and makes the extended timing pattern with programmed logic timeslot n with m Hz …. Software also generates and transfer the information from EVG to EVR 360Hz pulse Id embedded timestamp Event codes BSA information Software maintains the timing pipeline

Beam Synchronous Acquisition Beam Synchronous Acquisition (BSA): Acquire all beam-dependent scalars across multiple IOCs on the same pulse over multiple pulses of a certain kind (not just x-pulses- in-a-row) up to 120Hz. Acquire up to 2800 values per scalar in one acquisition request. Each value of the 2800 values can be an average of up to 1000 values. Each acquisition request can specify: Beam code (defines project, 1 = LCLS) Machine conditions of interest – rate, TS, permits, etc Provide constant 1HZ beam-synchronous data for channel archiver and displays

BSA data gethering BPM FEE Triggers Data I O C P N E T E V G E V R I O C CA Client CA Client EDEF Setup BSA Data EDEF Flags, Pattern, etc Timing Crate BPM Crate Data gathering part consists of the following actions: BSA event definition (EDEF) setup and start request done on the EVG IOC. 360hz checking on the EVG IOC with user notification when finished. 360hz requests (acquisition control) sent by the EVG IOC to all EVR IOCs via fast fiber optic link. Data checking, averaging, and array update per scalar record per request on the EVR IOCs. Data on EVR IOC must be available within 7.3 msec after beam or it will be lost, even when beam is less than 120hz. EDEF will finish with arrays that are not complete if this time budget cannot be met. For an acquisition at full beam rate (ie, 30hz), if data is acquired at a lower rate (ie, 10hz), the array will not be complete. Use rate-limit bits as-needed when setting up the EDEF. Implementation is all EPICS record-based.

Pipeline, Pattern & Event Code EVG EVR Step 5 Pipeline Advancing in the EVR Generate New pattern at !3 pulses prior! Pipeline Advancing in the EVG Fiber connection to EVR Trigger/Event Generation by the Event Code Dealing with the next1 pattern Pipeline index =1 is hard-coded in the database Decide event code list with the !Next1! pattern Re-construct EDEF data (for BSA) from the MOD5 & EDEF Masks Construct EDEF data (for BSA) from the MOD5 & EDEF Masks

AvgDone, Minor, Major, Init BSA & EDEF message EVG side Pattern for Next3 Modifiers TimeStamp EDEF masks + + AvgDone, Minor, Major, Init MOD5 for BSA masks (active) EVG&EVR do exactly same processing to update the EDEF table Fiber optic connection Step 5 EVR side Pattern Pipeline EDEF Table DEDEF 0 DEDEF 1 Update the EDEF table, after complete the pipeline advancing DEDEF n Timestamp (active) Timestamp (Init) avgDone flag Severity DEDEF 19

On going issue Switch PNET to VMTG (MTG) Due to the retirement of MPG in old control system VMTG only provides 360 Hz fiducial + timslot 0 which is synchronized with AC power line EVG software decided timing information/timing pattern which programmed by the evGui EVG software also decided pulse Id Pattern Bit Generator (PABIG) software module will do the timing pattern business in the EVG Keep use upper level EVG software

Software Stack for EVG EPICS DB EVG Application HW input bits in PABIG PNBN PVs from SoftIOC EPICS DB EDEF reservation for the BSA SNL program EVG Application HW input bits in PABIG Master Beam Control Bits 0 to 8 via CA GenVar PABIG PNET Task mpsComm Asyn module VMTG module EVG Drv/Dev udpComm Acromag DIO VMTG PNET 2nd NIC EVG MPS message (beam destination & Perm) BCS SBI Perm 360Hz Trigger BCS Beam Perm 476MHz Clock PNET broadcasting 119MHz Clock 360Hz Fiducial Trigger 360Hz Fiducial Trigger

Switch from PNET to VMTG PNET task need to be delayed ~ 150 usec after the PNET IRQ to wait the MPS message. PNET IRQ is using HW_TIMER to make the delay The PNET ISR implement 150 usec delay on the HW_TIMER The callback for the HW_TIMER releases signal to proceed the PNET Task. VMTG has configurable IRQ delay Configure the VMTG IRQ delay as ~570 usec The VMTG IRQ is occurred at 150 usec after the PNET IRQ Fiducial PNET VMTG Unknown delay PNET IRQ ISR implements the timer Timer callback releases the signal to the PNET task PNET task VMTG IRQ The ISR releases the signal to the PNET task ~150 usec ~ 570 usec MPS message arrives somewhere before the signal.

evGui Revolution from text base timing configuration to visual timing configuration

Future Plan and Issues (1) merge to main stream SLAC timing software has been diverse from community need to know, what is current status of new driver software need to know, what is future plan for firmware/register map need to get clear understanding, what is the SLAC specific features in the software BSA Timing Pattern Pipeline?

Future Plan and Issues (2) Support new platform Linux uTCA Some other new embedded platform including the EVR embedded in a FPGA Improvement for BSA more performance more easier/flexible configuration new requirements from physicists