PRALLEL CLIPPER The parallel configuration is defined as while the parallel variety has the diode in a branch parallel to the load.

EXAMPLE Determine the output voltage for the network shown in the fig.

SOLUTION Diode will be on for the –ve half cycle .So the effective circuit is shown in the fig.

SOLUTION Apply Id = 0, Vd =0 to get transition voltage so that Vi – IdR – 4V =0 Vi – 0R – 4V =0 Vi = 4V is transition voltage.

SOLUTION hence for the positive half cycle so that VL = V0 VL = 16 Volts.

EXAMPLE Consider in previous example the diode is silicon diode and draw its output.

SOLUTION The diode will be on for the negative half cycle. Apply Id=0 ,Vd = 0.7 to get transition voltage Vi + VT – V =0 Vi = V – VT =4 – 0.7 = 3.3 V

SOLUTION 3.3 is the transition voltage will be 4V, hence for positive half cycle VL = V0 V0 = 16V

CLAMPERS These are the circuits which clamp the input signal to a different level depending upon the configuration of the clamper circuit. For carrying out analysis following points to be remember

CLAMPERS The total swing of the output is equal to the total swing of the input signal. Start the analysis by considering that part of the input which will forward bias the diode. During the period, the diode is ‘ON’, assume that the capacitor will charge up instantaneously to a

CLAMPERS level determined by the network. (4) During the period for which the diode id ‘OFF’ assume that capacitor will hold its charge. (5) Throughout the analysis keep complete awareness of the polarity for V0, So that the proper value of Vo is determined.

EXAMPLE Determine v0 for the network shown in the fig.

SOLUTION Our analysis will begin at time t1 to t2 .our circuit will behave as shown in the fig. Applying KVL to input loop -20 + Vc – 5 =0 Vc = 25V

SOLUTION The capacitor will therefore charge up to 25V. In this case the resistor will not be shorted by the diode, but a Thevenin’s equivalent circuit for that portion of the

SOLUTION network which includes the battery and resistor will result in Rth = 0, with Eth = V = 5V. For the period t2 to t3 the circuit is shown in the fig.

SOLUTION KVL across the outer loop 10 + 25 – Vo = 0 And Vo = 35V

SOLUTION The time constant of the discharging network of fig. is determined by the product of RC and has magnitude T = RC = 0.01S

The output wave form will get the shape as

EXAMPLE Repeat the previous example using silicon diode with VT = 0.7V

SOLUTION For the short circuit state the network now takes the appearance of the fig. and V0 can be determined by KVL in the output section

SOLUTION +5 – 0.7 – V0 = 0 V0 = 4.3V

SOLUTION For the input section KVL will result in -20 +Vc + 0.7 – 5 =0 Vc =25 – 0.7 =24.3V

SOLUTION For the period t2 to t3 the network will now appear as in fig. By KVL 10 + 24.3 – V0 = 0 V0 = 34.3V