A 10. 6mW/0. 8pJ Power-Scalable 1GS/s 4b ADC in 0. 18µm CMOS with 5 A 10.6mW/0.8pJ Power-Scalable 1GS/s 4b ADC in 0.18µm CMOS with 5.8GHz ERBW Potential applications Ultra-Wide Band radio-receivers Wireless Personal Area Networks, Wireless Body Area Networks,… Energy-constrained portable devices Multi-rate reconfigurable systems Challenges High speed and large signal bandwidth Low power Power/performance configurability Exploit dynamic structures Our approach Improve Flash ADC architecture Power proportional to sampling rate UNIVERSITÀ DI PISA

The proposed flash ADC architecture Adopt dynamic comparators with built-in thresholds Power scales linearly with sample rate Remove unessential power-hungry blocks Preamplifiers (low) resistive ladder for reference generation Digital calibration enable trip-point tuning mitigate device mismatch

Performance summary Technology 0.18μm CMOS 1P6M 1.8V DNL / INL (Vin = 200mVptp) <0.25LSB / <0.17LSB Sampling Frequency 1GS/s DC ENOB 3.7 bit SNDR @ Nyquist 23.9dB Core area 420×50μm2 Design Power (mW) Res (bit) fsample (GS/s) ERBW (MHz) Process (μm) FoM (pJ) JSSC02 340 6 [5.7] 1.6 550 0.18 4 This design 10.6 4 [3.7] 1 5800 0.8 JSSC05 160 6 [5.5] 1.2 700 0.13 2.2 ISSCC04 10 6 [4.9] 0.6 300 0.09 0.54 ISSCC06 2.5 1.25 3300 0.16 Power scaling with fsample: 500MS/s  5.2mW (0.73pJ) VDD=1.7V, 200MS/s  2mW (0.67pJ)