Hugo França-Santos - CERN Pipelined ADC Hugo França-Santos - CERN

Pipelined ADC architecture For a resolution of 10 bit • 8 stages of 1.5 bits • 1 stage of 2 bits Analogue Input (n) Analogue Output (n) X2 Timing Generation 1.5 bit flash ADC 1.5 bit DAC CLK Phase2 Phase1 Analogue Input The speed of the ADC is limited by the rise-time of the operational amplifiers, the 1.5Bits per stage configuration is the faster one because is a multiplication by 2. (A gain of less that 2 can be used for very high-speed and low-resolution applications) The 1.5bit DACs are easy to build. Last stage resolution is to study: 2 or 3 bits? For 2 bits we need 3 comparators, for 3 bits we need 7 comparators. To be decided taking into account the transistor matching of the process. Stage 1 Stage 2 Stage 3 Stage 8 2-bit flash ADC 1.5 bit 2 bit 1.5 bit 1.5 bit 1.5 bit 10-bit Output Time Alignment & Digital Error Correction

Pipelined ADC architecture For a resolution of 10 bit • 8 stages of 1.5 bits • 1 stage of 2 bits

Pipelined ADC – Digital Correction 1 bit per stage 1.5 bit per stage 1100101011

Pipelined ADC – Digital Correction Ideal thresholds Thresholds with errors

Pipelined ADC – Latency

Pipelined ADC: Single stage How to distribute the time for the various blocks? Bad clocks will create distortions.

Pipelined ADC: FLASH ADC 1.5 Bits

Pipelined ADC: FLASH ADC 1.5 Bits output waveforms

Pipelined ADC: Latched comparator

Pipelined ADC: Single stage How to distribute the time for the various blocks? Bad clocks will create distortions.

Pipelined ADC: DAC 1.5 Bits

Pipelined ADC: Single stage How to distribute the time for the various blocks? Bad clocks will create distortions.

Pipelined ADC: Switched capacitor amplifier Timing to minimize distortions and charge injections Capacitors: small for fast settling and low power, big capacitors for thermal noise and better matching Low-resistance switches for fast settling but they inject more change

Floating Switch problem in Low-Voltage

Switch with channel charge injection cancellation Most simulation models are inaccurate in terms of charge injection. The fraction of the charge that exits through the source and the drain terminals is complex and depends on the impedance seen at each terminal to ground and the transition time of the clock. Using low or zero threshold transistors -> Worse control over the process, worse switch leakage

Pipelined ADC: Switched capacitor amplifier with charge cancellation

Pipelined ADC: Differential output operational amplifier Gain required for the resolution (only one amplifier or different ones for the different stages?) Gain and speed are booth important Gain boosting and stability CMFB Switched capacitor or not?

Pipelined ADC: Single stage How to distribute the time for the various blocks? Bad clocks will create distortions.

Pipelined ADC: Stage input-output

Specifications & Schedule High speed, high-resolution analogue to digital converter Resolution: 10 bits Speed: 40 MSPS Power: 30 mW (0.75 mW per MSPS) Area: 0.6 mm2 in a 0.13mm CMOS process Project Schedule December 2007 Schematics design complete March - April 2008 Layout ready -> Submission to foundry June - July 2008 Core ready -> Packaging July - August 2008 Chip ready -> Test at CERN

Thank you!