Motivation Combinational logic functions can be represented, and defined, by truth tables. Sequential logic function cannot, because their behavior depends.

Slides:



Advertisements
Similar presentations
Finite State Machine Continued
Advertisements

Lecture 13: Sequential Circuits
FSM Word Problems Today:
Traffic light contoller using FSM
Chapter #10: Finite State Machine Implementation
1 Combinational Logic Design&Analysis. 2 Introduction We have learned all the prerequisite material: – Truth tables and Boolean expressions describe functions.
TOPIC : Finite State Machine(FSM) and Flow Tables UNIT 1 : Modeling Module 1.4 : Modeling Sequential circuits.
COE 202: Digital Logic Design Sequential Circuits Part 3
Flip-Flops Computer Organization I 1 June 2010 © McQuain, Feng & Ribbens A clock is a free-running signal with a cycle time. A clock may be.
Lecture 22: Sequential Circuits Today’s topic –Clocks and sequential circuits –Finite state machines 1.
FSMs 1 Computer Organization I September 2009 © McQuain, Feng & Ribbens Motivation Combinational logic functions can be represented, and defined,
Our First Real System.
DISCUSSION CSE 140L 3 rd November 2010 Vikram Murali.
ECE C03 Lecture 101 Lecture 10 Finite State Machine Design Hai Zhou ECE 303 Advanced Digital Design Spring 2002.
Digital Circuit Review: Combinational Logic Logic operation –Need to know following two input gates: NAND, AND, OR, NOT, XOR –Need to know DeMorgan’s Theorems.
Fall 2007 L15: Combinational Circuits Lecture 15: Combinational Circuits Complete logic functions Some combinational logic functions –Half adders –Adders.
Contemporary Logic Design Finite State Machine Design © R.H. Katz Transparency No Chapter #8: Finite State Machine Design 8.5 Finite State Machine.
1 Lecture 14: FSM and Basic CPU Design Today’s topics:  Finite state machines  Single-cycle CPU Reminder: midterm on Tue 10/24  will cover Chapters.
Lecture 23 Design example: Traffic light controller.
11/10/ :53:59 AMweek12-3.ppt1 Intelligent Traffic Controller We want to use a finite state machine to control the traffic lights at an intersection.

1 COMP541 State Machines Montek Singh Feb 8, 2012.
Digital Logic Computer Organization 1 © McQuain Logic Design Goal:to become literate in most common concepts and terminology of digital.
Intro MIPS Computer Organization I 1 September 2009 © McQuain, Feng & Ribbens The Stored Program Computer 1945: John von Neumann – Wrote a.
Chapter 3 Digital Logic Structures. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 3-2 Complete Example.
DLD Lecture 26 Finite State Machine Design Procedure.
Finite State Machines This work is licensed under the Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License. To view a copy of this.
Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Topics n Sequential machine implementation: –clocking. n Sequential machine design.
Von Neumann Model Computer Organization I 1 September 2009 © McQuain, Feng & Ribbens The Stored Program Computer 1945: John von Neumann –
1 ENGG 1015 Tutorial Three Examples of Finite State Machines Supplementary notes Learning Objectives  Learn about Design of Finite State Machines Ack.:
Gates & Logic Computer Organization I 1 August 2009 © McQuain, Feng & Ribbens Logic Design Goal:to become literate in most common concepts.
More Intro MIPS Computer Organization I 1 September 2009 © McQuain, Feng & Ribbens Machine Language But, how is all of this driven? Machine.
Counters Computer Organization I 1 June 2010 © McQuain, Feng & Ribbens JK Flip-flop The JK flip-flop takes two data inputs and updates its.
Computer Organization CS345 David Monismith Based upon notes by Dr. Bill Siever and notes from the Patterson and Hennessy Text.
A stop sign is a traffic sign that stands for coming to a complete stop at an intersection or end of the road.
Computer Architecture Lecture 5 Sequential Circuits Ralph Grishman September 2015 NYU.
Finite State Machine. Clock Clock cycle Sequential circuit Digital logic systems can be classified as combinational or sequential. – Combinational circuits.
Appendix B The Basics of Logic Design
1 Lecture 13: Sequential Circuits, FSM Today’s topics:  Sequential circuits  Finite state machines  Single-cycle CPU Reminder: midterm on Tue 10/20.
Finite State Machines Mealy machine inputs Outputs next state function
Dr.Ahmed Bayoumi Dr.Shady Elmashad
Lecture 4. Sequential Logic #2
AS Computer Studies Finite State Machines 1.
The Stored Program Computer
The Simulation of Traffic Patterns and Optimizing Traffic Lights
Introduction CPU performance factors
COMP541 Sequential Logic – 2: Finite State Machines
Appendix B The Basics of Logic Design
EECE 5117C/6017C Lab 2 Traffic Light Controller using FSM
Boolean Algebra A Boolean algebra is a set B of values together with:
ELEC 1041 Digital Electronics Tutorial: Word Problems
Digital Signals Digital Signals have two basic states:
Lecture 13: Sequential Circuits, FSM
Lecture 13: Sequential Circuits, FSM
Analysis of Synchronous Sequential Circuits
Chapter Five The Processor: Datapath and Control
Introduction to Sequential Circuits
Analysis of Synchronous Sequential Circuits
Lecture 17 Logistics Last lecture Today HW5 due on Wednesday
Logic Gates.
Sequential logic implementation
Lecture 24 Logistics Last lecture Today HW7 back today
Motivation Combinational logic functions can be represented, and defined, by truth tables. Sequential logic function cannot, because their behavior depends.
Lecture 17 Logistics Last lecture Today HW5 due on Wednesday
EGR 2131 Unit 12 Synchronous Sequential Circuits
Finite State Machine Continued
Lecture 4 Sequential units. Registers
Midterm.
Clocks A clock is a free-running signal with a cycle time.
Multiplexor A multiplexor is a device that takes a number of data inputs and selects one of them to pass through as its output. The interface of a multiplexor.
Presentation transcript:

Motivation Combinational logic functions can be represented, and defined, by truth tables. Sequential logic function cannot, because their behavior depends upon both the state of their inputs and their current state. Implementing the control logic for a CPU will require using sequential logic functions, and we need a tool to express and model those functions mathematically. CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens

Finite State Machine A finite state machine (FSM) is… - a finite set of states Q = {S0, S1, . . . , SN}, and - a set of possible input values I = {i0, i1, . . . , iK}, and - a set of possible output values O = {o0, o1, . . . , oM}, and - a next state function F:QxIS, and - an output function G:QxIO The next state function maps the current inputs and the current state the next state of the FSM. The output function maps the current state and possibly the current inputs to a set of asserted outputs. CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens

Simple Example Here's a simple FSM representing a basic digital function. We have: Q = {E, O} I = {0, 1, end} O = {'E', 'O'} What's the next state function? What does it DO? E O start halt 1 end/E end/O Current State Input Next State Output E 1 O end halt 'E' 'O' CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens

Traffic Light Controller Consider a traffic light (red/green only) at an intersection of a north-south street with an east-west street; there are two input signals: NScar: Indicates that a car is over the detector placed in the roadbed in front of the light on the north-south road (going north or south). EWcar: Indicates that a car is over the detector placed in the roadbed in front of the light on the east-west road (going east or west). The traffic light should change from one direction to the other only if a car is waiting to go in the other direction; otherwise the light should continue to show green in the same direction as the last car that crossed the intersection. CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens

Traffic Light Controller Output Signals There are two output signals: NSlite: When this signal is asserted (1), the light on the north-south road is green; when this signal is deasserted (0), the light on the north-south road is red. EWlite: When this signal is asserted (1), the light on the east-west road is green; when this signal is deasserted (0), the light on the east-west road is red. Arguably, it is acceptable if both output signals are deasserted at the same time, but clearly they must never both be asserted at the same time. CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens

Traffic Light Controller States We need two states: NSgreen: the traffic light is green in the north-south direction EWgreen: the traffic light is green in the east-west direction CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens

TL Controller Schematic CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens

TL Controller Next-State & Output Fns Inputs Current State NScar EWcar Next State NSgreen 1 EWgreen Outputs Current State NSlite EWlite NSgreen 1 EWgreen CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens

TL Controller Next-State Analysis Inputs Current State NScar EWcar Next State NSgreen 0 NSgreen 1 EWgreen 1 EWgreen Let's represent the states NSGreen and EWGreen by 0 and 1, respectively. Then: CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens

TL Controller Output Analysis Outputs Current State NSlite EWlite 0 NSgreen 1 1 EWgreen CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens

TL Controller Implementation From slide #9 1-bit storage device CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens

Relationship to Hardware Common design issues in hardware control can be efficiently represented and analyzed using FSMs. CS@VT September 2009 ©2006-09 McQuain, Feng & Ribbens