Picosecond time measurement using ultra fast analog memories: new results since Orsay workshop. D.Breton & J.Maalmi (LAL Orsay), E.Delagnes (CEA/IRFU)

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Picosecond time measurement using ultra fast analog memories: new results since Orsay workshop. D.Breton & J.Maalmi (LAL Orsay), E.Delagnes (CEA/IRFU)

The USB_WaveCatcher prototype board Pulsers for reflectometry applications 1.5 GHz BW amplifier. Reference clock: 200MHz => 3.2GS/s Board has to be USB powered => power consumption < 2.5W µ USB Trigger input 2 analog inputs. DC Coupled. Trigger output +5V Jack plug Trigger discriminators SAM Chip Dual 12-bit ADC Cyclone FPGA This board was first designed for reflectometry applications. At the same time, we got involved in an worldwide picosecond working group. Analog memories seemed to be perfect candidates for precision measurements … => we decided to try to push the board’s performances to their maximum!

Examples of acquisitions: no off-line correction No offline correction except the subtraction of the fixed pedestal distribution Channel 0 Channel 1 Channel 0 Channel 1 75 mV amplitude, 1ns FWHM pulse. 3.2GS/s 2ns FWHM consecutive pulses, separated by 22ns, (300mV & 170mV amplitude). 3.2 GS/s -3dB 530 MHz The goal of the following study is to measure the board’s capacity to perform the measurement of the time difference between two pulses (like a TDC but directly with analog pulses !). Bode plot for 300mV pp Sinus

ENOB measurement gives a first information about jitter. ENOB is not Log( Max signal/Noise)/ Log(2) as often said. ENOB = (10 Log (sinus power / residues power) -1.76)/6.02. Depends on input sinewave frequency, noise & jitter. Contribution of jitter to ENOB = (-20 Log (2.π .σ .Fsine))-1.76)/6.02. σmeas consistent with 16ps rms 197 MHz sinewave/ 3.2GS/s ENOB curves simulated with a 300mVpp sinewave

Definition: Fixed Pattern Aperture Jitter Mismatches of elements in the delay chain induce: => dispersion of delay duration => error on the sampling time. Fixed for a given tap => “Fixed Pattern Aperture Jitter” Dispersion of single delays => time DNL. Cumulative effect => time INL. Gets worse with delay line length. Systematic effect => non equidistant samples (bad for FFT). => correction with Lagrange polynomial interpolation. Drawbacks: computing power. => good (and easy) calibration required. Real signal Fake signal After interpolation

Short and servo-controlled DL => Less Jitter (both kinds) Jitter vs DLL length 2 sources of aperture jitter: Random Aperture Jitter (RAJ). Fixed Pattern aperture Jitter (FPJ). Inside the DL the jitters are cumulative. Assuming there is no correlation: For RAJ, the aperture jitter @ tap j will be if σRd is the random jitter added by a delay tap For FPJ for a free running system if the total delay is servo-controlled if σFPd is the fixed pattern jitter added by a delay tap (σDNL) and N is the DL length. Short and servo-controlled DL => Less Jitter (both kinds)

Block diagram of clock distribution on the prototype Clean power supply FPGA OSC (200MHz) CPT1 Div/N USB interface (~ 20MHz) Test ? Backup Div CPT2 Div/M SAM Sync_reset N = 10 M = 20 ADC clock (~ 10MHz)

Extraction of fixed pattern and random jitter. Method: 135MHz-1.4Vpp sine-wave sampled by SAM Search of zero-crossing segment => length and position (cell). Higher frequency => 320-ps segments are not straight enough Lower frequency => more jitter because of noise Histogram of length[position]: propor. to time step duration assuming sine = straight line (bias ~ 1ps rms). mean_length[position] = fixed pattern effect => DNL => INL sigma_length[position] = random effect => Random Jitter (Sinewave is 197MHz on this plot)

Fixed pattern jitter DNL => mean segment lengths. Modulo 16 pattern. Integrated and fitted to measure the INL. After correction DNL DNL 2.1ps rms 9ps rms After correction INL INL ~1ps rms 16ps rms INL => segments have a modulo 16 pattern + slow pattern. Used for third degree Lagrange polynomial correction of data Advantage of servo-controlled structure: very small dependence to time and temperature

Random jitter Very encouraging random jitter floor ~ 2 ps rms After correction Very encouraging random jitter floor ~ 2 ps rms But peaks on “transition” samples up to ~20 ps (mean jitter ~3ps) Understood: due to the clock jitter, which can be seen only on the last cell of the DLLs The oscillator is supposed to deliver a clean clock = > probable source: the FPGA

First block diagram of clock distribution Clean power supply FPGA OSC (200MHz) CPT1 Div/N USB interface (~ 20MHz) Direct connection for the clock. Div CPT2 Div/M SAM Sync_reset N = 10 M = 20 ADC clock (~ 10MHz)

Fixed pattern jitter with direct clock connection DNL After correction DNL 0.5ps rms 6.6 ps rms After correction INL INL ~1ps rms 16 ps rms Slight improvement on DNL and INL …

Random jitter with direct clock connection Huge improvement on “transition” samples (now 3 to 3.5 ps max). => The FPGA indeed adds a lot of jitter to the clock ! => Mean jitter now ~ 2.2 ps rms …

But also … DNL & INL also randomly exhibit 3 different modulo 4 patterns at power-up ! Example: DNL INL It took us a certain amount of weeks to understand the problem ! It is actually due to a coupling between the temporal structure of the current consumed by the PFGA core (+1.5V supply) and the SAM write clock ! Coupling location still remains uncertain. Probably inside the PCB power planes. Now, how to get rid thereof ? …

First block diagram of clock distribution Clean power supply FPGA OSC (200MHz) CPT1 Div/N USB interface (~ 20MHz) Div CPT2 Div/M SAM Sync_reset The modulo changes with N and M … => Idea: flattening the core supply current structure => no common divisor to N and M. ADC clock (~ 10MHz) N = 11 M = 21

Fixed pattern jitter with N=11 and M=21 After correction DNL DNL 0.33ps rms 7.5 ps rms After correction INL INL 1.15ps rms 16.9ps rms No big difference in DNL and INL !

Random jitter with N=11 and M=21 1.95ps rms => but no more modulo patterns !!! Now the results are perfectly reproducible The INL correction seems to be stable over a long period of time (days at least) could be stored in EEPROM on-board like the cell pedestals The correction works rather well for other input frequencies between 100 and 200MHz, with a residual INL always remaining below 2.5ps. => this validates the correction method.

Block diagram of clock distribution on the new board Clean power supply FPGA OSC (200MHz) CPT1 Div/N USB interface (~ 20MHz) Fe=3.2GHz Div CPT2 Div/M SAM Sync_reset N = 11 M = 21 ADC clock (~ 10MHz) + careful redesign of the PCB.

Timing measurement with two pulses. Source: asynchronous pulse summed with itself reflected at the end of an open cable. Time difference between the two pulses extracted by crossing of a fixed threshold determined by polynomial interpolation of the 4 neighboring points (on 3000 events). Δt ~ 11ns σ = 10.9ps rms Vth Δt ~ 21ns σ = 11.4ps rms Vth σΔt ~ 11ps rms => jitter for a single pulse = 8 ps !

Summary of the board performances. 2 DC-coupled 256-deep channels with 50-Ohm active input impedance ±1.25V dynamic Range, with full range 16-bit individual tunable offsets 2 individual pulse generators for reflectometry applications. On-board charge integration calculation. Bandwidth > 500MHz Signal/noise ratio: 11.9 bits rms (noise = 630 µV RMS) Sampling Frequency: 400MS/s to 3.2GS/s Max consumption on +5V: 0.5A Absolute time precision in a channel (typical): without INL calibration: 20ps rms (400MS/s to 1.6GS/s) 16ps rms (3.2GS/s) after INL calibration 12ps rms (400MS/s to 1.6GS/s) 8ps rms (3.2GS/s) Relative time precision between channels: still to be measured. Trigger source: software, external, internal, threshold on signals Acquisition rate (full events) Up to ~1.5 kHz over 2 full channels Acquisition rate (charge mode) Up to ~40 kHz over 2 channels Acquisition software with graphical interface is under development

R&D on a ps TDC in IBM 130nm technology We are collaborating to the design of a new TDC in the IBM 130nm technology This is a collaboration between the University of Chicago, Orsay and Saclay The goal is to reach the ps precision thanks to the addition to an usual DLL-based TDC of analog memories sampling at very high frequency (20GS/s). Input clock frequency should be 312.5 MHz. A first prototype has been submitted by our colleagues of Chicago in June 2009 => it includes all the elements of a measurement channel except the discriminator. In the near future, we aim at building a 16-channel chip. Critical path for time measurement

Conclusion We designed a USB board to push the SAM chip (ultra fast analog memory) towards its limits. Timing measurements showed a resolution of ~16 ps rms without time INL correction, and less than 10ps after correction (SAM wasn’t even designed to this end !). The board (version 2) will soon (we start within one hour !) be tested with MCPPMT’s for low-jitter light to time conversion on Jerry’s test bench. The first boards of the last version (3) arrived last week. Tests showed us that analog memories look perfectly suited for ps time measurement. => no need for analog to digital pulse conversion, low power and low cost ! A new 130-nm pico-second TDC using ultra-fast analog memories is under design. This generic chip would probably not be usable directly on SuperB => A dedicated circuit would have to be designed for our forward PID.