Lecture 11 – Designing a simple computer 2017.06.26 King: Young Lady, look along the road and tell me if you can see either of my messengers. Alice: I see nobody on the road. King: I only wish I had such eyes. To see nobody, at such a distance, too! It's enough for me to see real people by this light. from Through the Looking-Glass, and What Alice Found There by Lewis Carroll (Charles Lutwidge Dodgson), 1871. © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Assignment Read textbook chapters 6 and 7 Midterm on Monday, July 3 covers Textbook chapters 1-7 Labs 00-04 HW 01-03 Lectures 01-14 8:30-9:30am in MATH 175 More information to come © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Announcements Due June 29: if you wish a DRC environment for midterm, Provide me your Letter of Accommodation, and Request DRC time for July 3 © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Design a Simple Computer We are moving up the levels of abstraction in the computing platform “Bare metal” computer :=: Arithmetic and logic unit (ALU), Multiplexers, Registers, Memory Function units :=: full adder, decoder, flip-flop Logic device :=: gates Electronic device :=: transistor This follows the trend in abstraction from Lab 01 to 02 to 03 Transistor Gate Adder, Flip-Flop Arithmetic Logic Unit; Register; Memory LOAD (memory referencing instruction) and ADD (register referencing instruction) shows the bleed through between levels of abstraction (HW to SW): If HW wasn’t such a WIMP then all memory would be as fast as registers and as fast as the ALU and ADD would reference MEMORY directly instead of a proxy for memory (in very early computers this was what happened). © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Components of a computer Useful decomposition of computer components for design considerations: input and output (I/O), memory, and data path and control (processor) Key design quality concerns: user, delight, translation, performance Performance Evaluation Program Translation Processor Memory User Instructions Input Control Operands Results  ALU Output Delight © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Necessary basics Input – cannot compute without telling computer what to do Output – cannot know what computer did without output Operations – execution is about performing operations Programmed decision making – execution is much more powerful if the computer can make decisions © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

First focus – the data path (Chapter 6) Design a circuit to perform 1) Fetch instructions 2) Locate and read operands 3) Execute instructions 4) Write results into specified location © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Good design practice: 1 step at a time Design requires considering many options, making many trade offs Dividing a system design into a collection of subsystem design tasks is helpful Data path circuit must accomplish 4 tasks, so start with Task 1: Fetch instructions For a stored program computer, Fetch must mean “read from memory” Instructions means? The instruction set The instruction representation, or format © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Choose the instruction set Chapter 6 develops an instruction set with four operations (a tiny, instructive example) © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Example of using the instructions Writing a program using these instructions is programming in assembly language; example Assembly instr. ; Comments load r2, 20(r1) ; r2  Data_Memory[20+r1] load r3, 24(r1) ; r3  Data_Memory[24+r1] add r4, r2, r3 ; r4  r2 + r3 store r4, 28(r1) ; Data_Memory[28+r1]  r4 jump 60(r7) ; Fetch at Instr._Memory[60+r7] r1, r2, r3, r4 are registers in the data path 20, 24, 28 are decimal constants “x ” means “x” is the location for the result Memory[x] means the contents of memory at address x + means addition, with operand type defined by the instruction (r1 + r2 is add with different data type than 28+r3) © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Define the instruction representation Example develops 4 instructions, but let’s imagine that our little computer might have up to 32 instructions, has 16 registers, and offers load and store instructions that are as powerful as possible uses 32-bit instructions, 32-bit default integer size, and 32-bit memory addresses These four design choices are enough to fully define the instruction representation, or format © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

How the design choices set the format “Up to 32 instructions” requires sufficient opcode bits to name ≤ 32 operations, implies use of 5 bits because “up to 32” ≤ 2^5 and it is wasteful to have excess bits in a format 16 registers requires 4-bit addresses to point to each register individually “Powerful load and store” requires use of largest possible range of included constants, implies “give all the rest of the bits to them” “Use 32-bit instructions” means the above fits in 32 bits © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Design choices and ethos: lower level “32-bit processor” refers to the number of bits handled at one time by the hardware in one or more key components of the processor. Let’s choose which key components: 32-bit (size) addresses, each pointing to a byte Want to have 32 wires to move addresses fast [speed Fetch operation]: feasible number of wires 232 locations in memory: enough to hold practical programs & data sets [speed Fetch] [Insufficient addressable memory is a very effective way to make a computer obsolete] 23 bits per memory location: native char data type Draw a box to hold the wordOutdated I/O is another effective way to make a computer obsolete. We are talking about design, so obsolescence is an important issue. © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Choosing opcode “names” Each instruction has an opcode or a “name” in the form of a specific pattern of a binary string These patterns will be used by the circuit to control the action of the circuit Lab 03 circuit controls Green, Yellow, Red lights Counter bits or decoder bits can control Yellow LED Control easy or difficult depending on bits chosen Opcode bit pattern choices can be easier or more difficult to use as input to control circuit; designers go for easy © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Instruction format Preceding design goals, constraints, and opcode choices translate into this format ______ _____ _____ _____ ______________________ 5 bits 4 bit 4 bit 4 bit 15 bits (all the rest) © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Assembly code and its machine code Data path circuit cannot process assembly add r4, r2, r3 ; r4  r2 + r3 Assembly converted, not translated, to machine code by the Assembler, result here is Seeing “Nobody” in the instruction Opcode PointerPointerPointer Unused offset, arbitrarily set all 0 © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

How are instructions stored in memory? Memory is a 1-dimensional array of storage locations, one location after another, sequential Programs are sequences of statements, 1-dimensional Simplest storage strategy: Store instructions in sequential memory locations Performance evaluation: Computing the address of the next location in a sequence requires only adding a fixed increment [simple and fast] Next location function must be able to create any 32-bit address; an essential property if instructions to be allowed anywhere in memory [Von Neumann] © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Time to: 1) Fetch instructions Instructions are in memory; fetch means Processor Control  Memory[address of instruction] Need a circuit that can hold (remember) and output a 32-bit address: 32-bit register Memory is addressed byte-by-byte Next fetch address of a 32-bit (4-byte) instruction will be at Current instruction address + 4 © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Fetch circuit – automating straight-line code 32 wires carrying the value Current_instruction_pointer + 4, also known as the Default_next_instruction_pointer Register that holds the pointer to (address of) the location in memory of the instruction to be fetched, also known as the current instruction 32 / 32 / 32 / 32 / Amount to add to point to next instruction given the design choice of a fixed-size, 4-byte instruction format AND byte-addressed memory Symbol for adder 32 / This symbol actually represents many wires much of the time (abstraction). For clarity, we label the number of wires. There are no explicit types in hardware; you have to figure out the data type by context and thinking. 32 wires that, at least, connect to the address input of instruction memory © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Fetch circuit as a sequential circuit State register Clock Combina-tional logic, 32-bit adder Register Clock Circuit components in orange have been abstracted out of Chapter 6 textbook figures Program counter, which functions as the Current_instruction_pointer © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Include instruction memory Input a pointer, a bit string to be interpreted as an address Get a copy of the bit string at the location pointed to by address, to then interpret as an instruction © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Add more control – decode instruction Interpret all fields of instruction format and generate logic signals to tell the data path circuit what to do A well-considered instruction format design makes decoding easier Very easy decoding for our textbook example, just partition the bit fields of the format © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Decode implemented by grouping wires Constant Pointer 32 / 32 / 32 / 32 / 4 / Pointer Wires grouped by instruction format fields. Control functions to occur are: • Pointing (3 instances, 4 bits each), • Value delivery (offset, 15 bits), • Operation selection for arithmetic/logic unit (ALU) (opcode, 5 bits) Instruction 4 / Pointer Pointer, or address Address, or pointer 4 / Pointer 32 / 15 / Value / 5 Control bits © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Time to: 2) Locate and read operands Operands per instruction format are reg A, reg B, and offset which are, respectively pointer, pointer, and value Pointer bit strings should be delivered to the address input(s) of a memory, which in turn outputs bit string(s) that, if delivered to the ALU, will be interpreted as operand(s) Value bit strings should be sent directly to the ALU © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Register Unit Special, fastest memory Contains 16 32-bit registers Inputs Three 4-bit addresses for reg A, reg B, dst reg because 1 instruction may access 3 registers One 32-bit result value bit string, when write enabled 1-bit Write_Enable control signal (abstracted out in textbook figures) Outputs Copies of the 32-bit contents of any 2 of 16 registers, including duplicating contents of one register to both outputs © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Read operands, completing Fetch Copy of 15-bit value direct to ALU 5 bits of control signals direct to ALU © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Time to: 3) Execute instructions Execution circuit (ALU) supports all instructions What does each instruction ask of the ALU? Breaking the execution design into subsystems ADD: add two values coming from reg A and reg B LOAD: add Offset to a Reg value STORE: add Offset to a Reg value JUMP: add Offset to a Reg value Ignoring memory access for now Design for Offset + reg A (could choose reg B) How ADD with reg B, yet L/S/Jump with Offset? © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Arithmetic./Logic Unit (ALU) in action Selected operand 32-bit regA value 32-bit regB value Opcode bits to control ALU 32-bit offset value Sign extend 15 bit offset in 2’s comp Mux circuit chooses 1 of 2^1 inputs to connect to ALU. Mux must receive a 1-bit signal controlling which of 2^1 inputs is selected. Control is abstracted out of this diagram. © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Time to: 4) Write results into specified location What are the results and where do they go? ADD: ALU output is result, deliver to dst reg JUMP: ALU output is Next_instruction_pointer, must deliver to Instruction_pointer_register LOAD: ALU output is pointer that must be sent to data memory, which then produces copy of the location contents which, finally, must be written into dst reg STORE: ALU output is pointer that must be sent to data memory along with the value from reg B to be written into the data memory location © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Put result where it belongs: ADD ADD result data path ADD: ALU output is result, deliver to dst reg; result has the meaning “integer” because this is an integer adder © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Put result where it belongs: LOAD LOAD result data path LOAD: ALU output is pointer that must be sent to data memory, which then produces copy of the location contents which, finally, must be written into dst_reg; Result is a bit string from memory: no inherent meaning at all © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Put result where it belongs: STORE STORE result data path STORE: ALU output is pointer that must be sent to data memory along with the value from reg B to be written into the data memory location; Result is a bit string from reg_B written in memory, no inherent meaning at all © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Put result where it belongs: JUMP JUMP result data path JUMP: ALU output is computed Next_instruction_pointer, must deliver to Instruction_pointer_register; Result meaning is location of next instruction on the execution path © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

Recall: Default_next_instruction_pointer Default_next_instruction_pointer computed after every fetch, by default; Result meaning is location of next instruction on the execution path © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra

All result paths, overlapped LOAD result data path JUMP result data path ADD result data path STORE result data path Input selected by Mux M3 and inputs selected by Mux M1 control where results are delivered (Mux control abstracted out) © 2017 by George B. Adams III Portions © 2017 Dr. Jeffrey A. Turkstra