ECE 4110–5110 Digital System Design

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Presentation transcript:

ECE 4110–5110 Digital System Design Lecture #9 Agenda VHDL : Structural Design Announcements n/a Lecture #9 Page 1

Structural Design Structural Design - we can specify functionality in an architecture in two ways 1) Structurally : text based schematic, manual instantiation of another system 2) Behaviorally : abstract description of functionality - we will start with learning Structural VHDL design Components - blocks that already exist and are included into a higher level design - we need to know the entity declaration of the system we are calling - we "declare" a component using the keyword "component" - we declare the component in the architecture which indicates we wish to use it Lecture #9 Page 2

Structural Design Component Syntax component component-name port (signal-name : mode signal-type; signal-name : mode signal-type); -- exactly the same as the Entity declaration without the keyword is end component; Let's build this… Lecture #9 Page 3

Structural Design Component Example - let's use these pre-existing entities "xor2" & "or2" entity xor2 is port (In1, In2 : in STD_LOGIC; Out1 : out STD_LOGIC); end entity xor2; entity or2 is port (In1, In2 : in STD_LOGIC; Out1 : out STD_LOGIC); end entity or2; Lecture #9 Page 4

Structural Design Component Example - now let's include the pre-existing entities "xor2" & "or2" into our "TOP" design entity TOP is port (A,B,C : in STD_LOGIC; X : out STD_LOGIC); end entity TOP; architecture TOP_arch of TOP is component xor2 -- declaration of xor2 component port (In1, In2 : in STD_LOGIC; Out1 : out STD_LOGIC); end component; component or2 -- declaration of or2 component port (In1, In2 : in STD_LOGIC; Out1 : out STD_LOGIC); end component; begin ….. Lecture #9 Page 5

Structural Design Signals - now we want to connect items within an architecture, we need "signals" to do this - we defined signals within an architecture Internal "Signal" Internal "Components" Lecture #9 Page 6

Structural Design Signal Syntax architecture TOP_arch of TOP is signal signal-name : signal-type; signal signal-name : signal-type; Lecture #9 Page 7

Structural Design Let's put the signal declaration into our Architecture - now let's include the pre-existing entities "xor2" & "or2" into our "TOP" design architecture TOP_arch of TOP is signal node1 : STD_LOGIC; component xor2 -- declaration of xor2 component port (In1, In2 : in STD_LOGIC; Out1 : out STD_LOGIC); end component; component or2 -- declaration of or2 component port (In1, In2 : in STD_LOGIC; Out1 : out STD_LOGIC); end component; begin ….. end architecture TOP_arch; node1 Lecture #9 Page 8

Structural Design Component Instantiation - after the "begin" keyword, we can start adding components and connecting signals - we add components with a "Component Instantiation" syntax: label : component-name port map (port => signal, ……) ; NOTE: - "label" is a unique reference designator for that component (U1, INV1, UUT1) - "component-name" is the exact name as declared prior to the "begin" keyword - "port map" is a keyword - the signals with in the ( ) of the port map define how signals are connected to the ports of the instantiated component Lecture #9 Page 9

Structural Design Port Maps - There are two ways describe the "port map" of a component 1) Positional 2) Explicit Positional Port Map - signals to be connected to the component are listed in the exact order as the components port order ex) U1 : xor2 port map (A, B, node1); Explicit Port Map - signals to be connected to the component are explicitly linked to the port names of the component using the "=>" notation (Port => Signal, Port => Signal, ….) ex) U1 : xor2 port map (In1 => A, In2 => B, Out1 => node1); Lecture #9 Page 10

Structural Design Execution - All components are executed CONCURRENTLY - this mimics real hardware - this is different from traditional program execution (i.e., C/C++) which is executed sequentially because We are NOT writing code, we are describing hardware!!! Lecture #9 Page 11

Structural Design Let's put everything together architecture TOP_arch of TOP is signal node1 : STD_LOGIC; component xor2 -- declaration of xor2 component port (In1, In2 : in STD_LOGIC; Out1 : out STD_LOGIC); end component; component or2 -- declaration of or2 component port (In1, In2 : in STD_LOGIC; Out1 : out STD_LOGIC); end component; begin U1 : xor2 port map (In1=>A, In2=>B, Out1=>node1); U2 : or2 port map (In1=>C, In2=>node1, Out1=>X); end architecture TOP_arch; U1 node1 U2 Lecture #9 Page 12