EEE4084F Digital Systems NOT IN 2017 EXAM Lecture 25

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Presentation transcript:

EEE4084F Digital Systems NOT IN 2017 EXAM Lecture 25 RC Platform Case Studies 2/2: Large & small FPGA-based RC systems NOT IN 2017 EXAM Microprocessor-based: The Cell Broadband Engine Architecture, IBM Blade FPGA-based: PAM, VCC, SPLASH … (this lecture) (previous lecture) Lecturer: Simon Winberg Attribution-ShareAlike 4.0 International (CC BY-SA 4.0)

Lecture Overview Large-scale FPGA-based RC system examples PAM, VCC, Splash Small-scale FPGA-based RC system examples PRISM Algotronix CAL, XC620, Cray Research XD1, SRC Silicon Graphics RASP

Large-scale RC Systems A look at platforms architectures

Large RC System - PAM Programmable Active Memories (PAM) Produced by Digital Equipment Corp (DEC) Used Xilinx XC3000 FPGAs Independent banks of fast static RAM SRAM SRAM SRAM SRAM Host CPU FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA DRAM SRAM SRAM SRAM SRAM Digital Equipment Corp. PAM system (1980s) Image adapted from Hauck and Dehon (2008) Ch3

Large RC System - VCC Virtual Computer Corporation (VCC) First commercially commercial RC platform* Checkerboard layout of Xilinx XC4010 devices and I-Cube programmable interconnection devices SRAM modules on the edges SRAM FPGA FPGA FPGA FPGA … FPGA FPGA SRAM SRAM FPGA I-Cube FPGA I-Cube … I-Cube FPGA SRAM … … … … … … … … SRAM FPGA I-Cube FPGA I-Cube … I-Cube FPGA SRAM VCC Virtual Computer * Hauck and Dehon (2008)

Large RC System - Splash Dev. by Super Computer Research (SCR) Center ~1990 Well utilized (compared to previous systems). Comprised linear array of FPGAs each with own SRAM * Summary of the Splash system Developed initially to solve the problem of mapping the human genome and other similar problems. Design follows a reconfigurable linear logic array. The SPLASH aimed to give a Sun computer better than supercomputer performance for a certain types of problems. At the time, the performance of SPLASH was shown to outperform a Cray 2 by a factor of 325. FPGAs were used to build SPLASH, a cross between a specialized hardware board but more flexible like a supercomputer. The SPLASH system consists of software and hardware which plugs into two slots of a Sun workstation. ** Illustration of the SPLASH design (adapted from *) FPGA FPGA … FPGA SRAM SRAM … SRAM SRAM FPGA Crossbar Dedicated controller FPGA FPGA … FPGA SRAM SRAM SRAM … * Hauck and Dehon (2008) SRC Splash version 2 **Adapted from: Waugh, T.C., "Field programmable gate array key to reconfigurable array outperforming supercomputers," Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991 , vol., no., pp.6.6/1,6.6/4, 12-15 May 1991 doi: 10.1109/CICC.1991.164051

Small-scale RC Systems A look at platforms architectures

Small RC Systems Algotronix Brown University’s PRISM Single FPGA co-processor in each computer in a cluster Main CPUs offloading parallelized functions to FPGA Algotronix Configurable Array Logic (CAL) – FPGA featuring very simple logic cells (compared to other FPGAs) Later become XC6200 (when CAL bought by Xilinx) * Hauck and Dehon (2008)

Reconfigurable Supercomputers Cray Research XD1: 12 processing nodes 6x ADM Opteron processors 6x Reconfigurable nodes built from Xilinx Vertex 4 Each XD1 in own chassis, can connect up to 12 chassis in a cabined (i.e. 144 processing nodes) SRC Traditional processor + reconfig. processing unit Based on Xilinx Virtex FPGAs Silicon Graphics RASP (reconfigurable application-specific processor) Blade-type approach of smaller boards plugging into larger ones Ref: Hauck and Dehon Ch3 (2008)

Additional Reading Reading Reconfigurable Computing: A Survey of Systems and Software (ACM Survey) * (not specifically examined, but can help you develop insights that help you demonstrate a deeper understanding to problems) -- End of the Cell Processor case study -- * Compton & Hauck (2002) .“Reconfigurable Computing: A Survey of Systems and Software” In ACM Computing Surveys, Vol. 34, No. 2, June 2002, pp. 171–210.

Conclusion & Plans Reading Next lecture: Hauck, Scott (1998). “The Roles of FPGAs in Reprogrammable Systems” In Proceedings of the IEEE. 86(4) pp. 615-639. Next lecture: Amdahl’s Law Discussion of YODA phase 1

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