ADPCM Adaptive Differential Pulse Code Modulation Team M4 Andrew Akindele Edward Shim James Lee Anthony Xu Project Objectives Stage 6 Component Layout (Corrected) Design and implement an Adaptive DPCM Manager : Joe Bakker Date March 3rd, 2003 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Project Status Done C and Verilog Coding Schematics Gate Level Layout Functional Block Layout (98%) Functional Block Simulations (98%) Component Correction and Optimization More Accurate Floorplanning Next Chip Wiring Simulations and Verification 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project New Design Decisions Added Some Buffers Registers ROM tables Multiplexers Macro Blocks Just schematics 18-525 Integrated Circuit Design Project

Carry Lookahead Adder (OLD) Dim: 162.25 x 139.2 Transistors 814 Density 0.036 tr/um2 18-525 Integrated Circuit Design Project

Carry Lookahead Adder (OLD) Tprop = 6.034ns 18-525 Integrated Circuit Design Project

Carry Lookahead Adder (NEW) Dim: 143.9 x 100.15 Transistors 956 Density 0.066 tr/um2 18-525 Integrated Circuit Design Project

16-bit Register (NEW) With Write Enabled Dim: 126.9 x 37.2 ; Transistors 328 ; Density 0.069 tr/um2 18-525 Integrated Circuit Design Project

16-bit Register (NEW) Without Write Enabled Dim: 76.1 x 39.15 ; Transistors 224 ; Density 0.075 tr/um2 18-525 Integrated Circuit Design Project

16-bit Register (write_en) Trise = 0.35ns Tfall = 0.19ns Tprop = 1.05ns FGOOD = 333MHz 18-525 Integrated Circuit Design Project

8-bit Register (NEW) With Write Enabled Dim: 65.3 x 37.2 ; Transistors 164 ; Density 0.068 tr/um2 18-525 Integrated Circuit Design Project

8-bit Register (NEW) Without Write Enabled Dim: 38 x 35.4 ; Transistors 112 ; Density 0.083 tr/um2 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project ROMstep (OLD vs. NEW) Dim: 172.85 x 74.1 Transistors 1,791 Density 0.138 tr/um2 Dim: 172.85 x 81.8 Transistors 1,855 Density 0.131 tr/um2 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project ROMstep Tprop = 2.74ns 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project 21mux-16bits (OLD vs. NEW) Dim: 157.3 x 8.6 ; Transistors 96 ; Density 0.071 tr/um2 Dim: 99.9 x 16.3 ; Transistors 104 ; Density 0.064 tr/um2 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project 21mux-8bits (OLD vs. NEW) Dim: 78.9 x 8.6 ; Transistors 48 ; Density 0.071 tr/um2 Dim: 51.45 x 16.3 ; Transistors 52 ; Density 0.062 tr/um2 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project 21mux-4bits (OLD vs. NEW) Dim: 39.7 x 8.6 ; Transistors 24 ; Density 0.070 tr/um2 Dim: 47.15 x 8.6 ; Transistors 28 ; Density 0.069 tr/um2 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project FSM (NEW) Dim: 61.3 x 39.6 ; Transistors 141 ; Density 0.058 tr/um2 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Ripple Carry Adder Tprop-LOW = 0.767ns 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Ripple Carry Adder Tprop-HIGH = 3.415ns 18-525 Integrated Circuit Design Project

Component Simulations New tprop high Old tprop high New tprop low Old tprop low ROMstep 2.74ns 4.09ns 2.72ns 2.56ns CLA 16-bit 6.034ns RCA 8-bit 3.415ns 0.54ns 0.77ns 1.01ns FSM FGOODnew = 333Mhz FGOODold = 250Mhz Clamp_index 1.76ns 1.61ns 1.64ns 1.84ns Register tprop high = 0.91ns tprop low = 1.05ns FMAX = 333Mhz 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Component Numbers Component New Trans. Old New Dim. Old Dim. Density C.L. Adder 956 814 143.9x100.2 162.3x139.2 0.066 Reg. 16-bits(w) 328 304 126.9x37.2 0.069 Reg. 16-bits 224 208 76.1x39.2 0.075 Reg. 8-bits (w) 164 156 65.3x37.2 0.068 Reg. 8-bits 112 100 38.0x35.4 0.083 ROMstep 1,855 1,791 172.9x81.8 172.9x74.1 0.131 Mux 16-bits 104 96 99.9x16.3 157.3x8.6 0.064 Mux 8-bits 52 48 51.6x16.3 78.9x8.6 0.062 Mux 4-bits 28 24 47.2x8.6 39.7x8.6 FSM 141 137 61.3x39.6 0.058 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Macro Blocks Sub-mux 16bit subtractor 16bit – 2to1 mux Diff-step Sub-mux-inv inverter Add-mux 16bit adder 18-525 Integrated Circuit Design Project

Detailed Floorplan (v.1) Dimensions: 500 x 480 18-525 Integrated Circuit Design Project

Detailed Floorplan (v.2) Dimensions: 450 x 480 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Questions? 18-525 Integrated Circuit Design Project