Forschungszentrum Informatik, Karlsruhe Power Estimation Approach for SRAM- based FPGAs FZI Embedded System Design Group (ESDG) Karlheinz Weiss, Thorsten Steckstor, Wolfgang Rosenstiel FZI Forschungszentrum Informatik at the University of Karlsruhe

2 Forschungszentrum Informatik, Karlsruhe Overview Introduction – State of the art Estimating Power Consumption for Virtex – technology power factor K p(Virtex) – benchmark test design SPYDER-System – SPYDER-VIRTEX-X2 – SPYDER-CORE-P2/SH3 (7709A/7729-DSP) Experimental Results Current work in progress – SPYDER-VIRTEX-X2E

3 Forschungszentrum Informatik, Karlsruhe Introduction FPGA development in the last few years – significant increase in on-chip gate capacity – decrease in run-times through programmable logic Dramatically increase of the power consumption – circuit speed (in terms of average clock frequency) – utilized chip area (in terms of CLBs, routing length and IOs) Problems for embedded system design – FPGAs can consume several amperes of current – appropriate board design for power supply is needed – sufficient ambient conditions to carry of the heat must be provided Solution: – Estimation of power consumption in an early design step

4 Forschungszentrum Informatik, Karlsruhe State of the Art: XC4000 architecture P EST = P STAT + P IO + P INT – P STAT : static power (few microwatts) – P IO = P DC + P AC : IO-power – P INT : internal power (important) >> K p(Virtex) ??

5 Forschungszentrum Informatik, Karlsruhe Estimating Power for Virtex P INT : measured on SPYDER-VIRTEX-X2 V Core := 2.5 V f Max : constrain from the development tool N LC := 2.25 x n Slice (output development tool) Tog LC : can be set to 1

6 Forschungszentrum Informatik, Karlsruhe SPYDER-System

7 Forschungszentrum Informatik, Karlsruhe C-API-Routines for NT 4.0 connection to CORE-tools SPYDER-VIRTEX-X2: architecture PCI - SLOT PCI-interface PLX-PCI9080 Xilinx-Virtex-FPGA XCV300...XCV800 BGA 432 arbiter CPLD XC95144xl Configuration- Flash 2M x 8 external FPGA configuration header (parallel port) extension header I and II high density logic analyzer connectors I II configuration power supply + 2,5V or 1,8V / 10A + 3,3V / 3A microcontroller SSRAM 256k x 32 or SDRAM 4M x 32 SSRAM 256k x 32 or SDRAM 4M x 32 Memory Add-On Board 4M x 32 SDRAM or 256k x 32 SSRAM or 1M x 32 Flash III Memory Add-On Board 4M x 32 SDRAM or 256k x 32 SSRAM or 1M x 32 Flash

8 Forschungszentrum Informatik, Karlsruhe Experimental Results smallmiddlelarge

9 Forschungszentrum Informatik, Karlsruhe Experimental Results Worst Case Scenarios

10 Forschungszentrum Informatik, Karlsruhe 86I II 86III 86 IV Xilinx Virtex FPGA (provide up to 2 mio. gates) XCV1000E up to XCV2000E BGA 560 SSRAM 256k x 32 or SDRAM 4M x 32 SSRAM 256k x 32 or SDRAM 4M x 32 scaleable in size Configuration SH3-7709A core 8MB Flash 100/10BaseT ethernet LAN/WAN Intra/Internet (TCP/IP) Current work: SPYDER-VIRTEX-X3E extension headers I to IV high density logic analyzer connectors 86I II 86III 86 IV Xilinx Virtex FPGA (provide up to 2 mio. gates) XCV1000E up to XCV2000E BGA 560 SSRAM 256k x 32 or SDRAM 4M x 32 SSRAM 256k x 32 or SDRAM 4M x 32 power supply + 2,5V or 1,8V / 10A + 3,3V / 3A not visible to the user back planes

11 Forschungszentrum Informatik, Karlsruhe Conclusion Estimating power consumption in an early design step – used the kown approach for XC4000 – extended that approach to the novel Virtex architecture Work was done using the SPYDER-tool set – especially SPYDER-VIRTEX-X2 – PCI-based Virtex-FPGA emulation platform Experimental Result – K p(Virtex) = 4.6 x – about 2.5 better than XC4000XV-family Current work: SPYDER-VIRTEX-X3E – Intra/Internet accessible

12 Forschungszentrum Informatik, Karlsruhe Picture of SPYDER-VIRTEX-X2 Further information: - user manual - application notes - support software download - IP-cores - all accepted papers of the ESDG You are invited to see a demonstration outside now!