Dept. of Electronics & Info. Eng. Prof. Jongbok Lee How to use ISE Dept. of Electronics & Info. Eng. Prof. Jongbok Lee

A. Introduction Xilinx ISE (Integrated Software Environment) VHDL/Verilog coding Synthesis FPGA Programming & Implementation

I. Start Double click Xilinx ISE 10.1i File New Project Project Navigator appears File New Project New Project window Project Name : proj_name Top-Level Module Type : HDL Click [next] File ***.ise is created

New Project window Device Family : Spartan3 Device : xc3s400 Package : FT256 Speed Grade : -4 [next][next][finish]

II. VHDL Coding Project  New Source ProjectAdd Source Select VHDL Module File Name : myinv ProjectAdd Source You can add an existing vhdl source Define VHDL Source window Port Name : Direction a: in b: out [next][finish]

if VHDL window appears, File  Save Source window:Source for Synthesis/Implementation You can double click Check Syntax and find the syntax error Architecture Behavioral of myinv is begin b <= not(a); end Behavioral

IV. Synthesis Source window : select Synthesis/Implementation signal B13 B14 A14 A12 Source window : select Synthesis/Implementation Synthesize-XST click Check Syntax if wrong, see the View Synthesis Report and fix it. if right Save FPGA pin number assigment Source window: select myinv.vhd Process window: User Constraints  Floor Plan IO - Pre Synthesis Xilinx PACE window appears Design Object List-I/O Pins I/O Name : I/O Direction : Loc a : Input :G3 b : Output :A12 File  Save G3 G4 H3 H4 signal pin no. a G3 b A12

Switches & LEDs on Board P16 D9 C9 C12 B13 B14 A14 A12 LED PUSH SWITCH DIP SWITCH G3 G4 H3 H4 R16 C15 B16 G14 G15 L13 M14 G1

Note In one project, only one module can be synthesized. if the User Constraint, Synthesize-XST,Implement, Generate menu does not appear in the process window, select module, click right mouse button and select to execute Set As Top Module Then the three triangle appears in front of the module.

Implementation Translate : transform the netlist into the inner format Map : optimize and then map the logic circuits to the FPGA resources such as CLB and IOB. Place & Route : connect the gates allocated in CLBs

note CLB(Configurable Logic Block) consists of 3 LUTs(Look Up Table) and 2 Flip Flops the basic block that constitutes FPGA

Synthesize and P&R Process window : double click Synthesize-XST Process window : double click Implement Design

EDA-Lab II Experiment Kit Function : An equipment for the verification of FPGA circuit design Usage : education, circuit development FPGA capacity : 400,000 gates Supporting software : Design Pro Shop

V. Emulation Emulation ? How to set up a hardware mimics another hardware How to set up connect EDA-Lab 2’s Xilinx USB JTAG port to PC. connect the power cable. Turn on the Power.

Generating an FPGA programming file Process window : Double click Generate Programming File See the Programming File Generation Report make sure myinv.bit has been created. It should be in the project folder.

iMPACT Process window Configure Target Device Manage Configuration Project(iMPACT) File  Initialize Chain Assign New Configuration File : myinv.bit [open] [bypass] select xc3s400 (left green one) and click the right mouse buttonprogram : Program Succeeded !

Emulation 입력 push button 1 누르지 않음 누름 출력 LED 꺼짐 1 켜짐 누름 출력 LED 꺼짐 1 켜짐 % 손을 떼면 입력 1- LED 꺼짐 출력 0, 누르면 입력- 0 LED 켜짐 출력 1

Emulation with DIP switch Try again with below pins for DIP switch R16 C15 B16 G14 G15 L13 M14 G1 입력 DIP switch 1 내림 올림 signal pin no. a R16 b A12

Emulation with DPS Try again with below pins for DPS Connect cables carefully Input : JP4.0~CN3.22 Output : JP6.0~CN1.17 Plug USB cable into the DPS-USB port. signal pin no. a D7 b A12

Emulation with DPS Execute DPS Down load DPS from the lecture site Double click DPS 3.5 and install View  Single Step Mode, input signals and click Write View  Waveform Mode, you can see the waves

View Multi Step Mode ToolOptionTiming Edit Add : lines appear(or click ‘+’ symbol). Input 16 digits either in Binary or Hexa. ex) 0000000000001000 or 0008 (which is simpler?) EditSelect All (or Ctrl-C). PortRun (or symbol ’’):automatically processes and outputs generated in binary and hexa. ToolOptionTiming Interval For Running 500ms may be changed.

Multi Step Mode I/O Hexa-decimal input and hexa-decimal output is recommended Without input, rest of the digits are filled with zero automatically.

DPS Emulation Result 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[2] Full Adder Data Flow Modeling (3 methods) entity full_adder is port (a,b,ci : in std_logic; sum, co : out std_logic); end full_adder; architecture Behavioral of full_adder is begin co <= (a and b) or (b and ci) or (ci and a); sum <= a xor b xor ci; end Behavioral; P16 D9 C9 C12 B13 B14 A14 A12 G3 G4 H3 H4 R16 C15 B16 G14 G15 L13 M14 G1 signal push DIP pin no. (DPS) cable a G3 R16 D7 JP4.0~CN3.22 b G4 C15 C7 JP4.1~CN3.23 ci H3 B16 B7 JP4.2~CN3.24 sum A12 JP6.0~CN1.17 co A14 JP6.1~CN1.18 % 실험 예 손을 모두 떼면 입력 111 LED on-on이므로 출력 11 두개를 누르면 입력 100 LED off-on이므로 출력 01 (sum=1) 한 개를 누르면 입력 110 LED on-off이므로 출력 10 (co=1) 세개를 누르면 입력 000 LED off-off 출력 00

DPS Emulation Result 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 FFFC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 FFFD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 FFFD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 FFFE 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 FFFD 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 FFFE 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 FFFE 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF