Day 12: October 1, 2012 Variation ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 12: October 1, 2012 Variation Penn ESE370 Fall2012 -- DeHon

Previously Understand how to model transistor behavior Given that we know its parameters Vdd, Vth, tOX, COX, W, L, NA … CGC CGCS CGCB Penn ESE370 Fall2012 -- DeHon

But… We don’t know its parameters (perfectly) Fabrication parameters have error range Identically drawn devices differ Parameters change with environment (e.g. Temperature) Parameters change with time (aging) Why I am more concerned with robustness than precision. Penn ESE370 Fall2012 -- DeHon

Today Sources of Variation Coping with Variation Fabrication Operation Aging Coping with Variation Margin Corners Binning Penn ESE370 Fall2012 -- DeHon

Fabrication Penn ESE370 Fall2012 -- DeHon

Process Shift Oxide thickness Doping level Layer alignment Growth and Etch rates and times Depend on chemical concentrations How precisely can we control those? Vary machine-to-machine, day-to-day Impact all transistors on wafer Penn ESE370 Fall2012 -- DeHon

Systematic Spatial Parameters change consistently across wafer or chip based on location Chemical-Mechanical Polishing (CMP) Dishing Lens distortion Penn ESE370 Fall2012 -- DeHon

FPGA Systematic Variation 65nm Virtex 5 [Tuan et al. / ISQED 2010] Penn ESE370 Fall2012 -- DeHon

Oxide Thickness [Asenov et al. TRED 2002] Penn ESE370 Fall2012 -- DeHon

Line Edge Roughness 1.2mm and 2.4mm lines From: http://www.microtechweb.com/2d/lw_pict.htm Penn ESE370 Fall2012 -- DeHon

Optical Sources What is the shortest wavelength of visible light? How compare to 45nm feature size? Penn ESE370 Fall2012 -- DeHon

Phase Shift Masking Today’s chips use λ=193nm Source http://www.synopsys.com/Tools/Manufacturing/MaskSynthesis/PSMCreate/Pages/default.aspx Penn ESE370 Fall2012 -- DeHon

Line Edges (PSM) Source: http://www.solid-state.com/display_article/122066/5/none/none/Feat/Developments-in-materials-for-157nm-photoresists Penn ESE370 Fall2012 -- DeHon

Intel 65nm SRAM (PSM) Source: http://www.intel.com/technology/itj/2008/v12i2/5-design/figures/Figure_5_lg.gif Penn ESE370 Fall2012 -- DeHon

Statistical Dopant Placement [Bernstein et al, IBM JRD 2006] Penn ESE370 Fall2012 -- DeHon

Random Trans-to-Trans Random dopant fluctuation Local oxide variation Line edge roughness Etch and growth rates Stochastic process Transistors differ from each other in random ways Penn ESE370 Fall2012 -- DeHon

Source: Noel Menezes, Intel ISPD2007 Penn ESE370 Fall2012 -- DeHon

Impact Changes parameters Change transistor behavior W, L, tOX, Vth W? Penn ESE370 Fall2012 -- DeHon

Example: Vth Many physical effects impact Vth Doping, dimensions, roughness Behavior highly dependent on Vth Penn ESE370 Fall2012 -- DeHon

Vth Variability @ 65nm [Bernstein et al, IBM JRD 2006] Penn ESE370 Fall2012 -- DeHon

Impact of Vth Variation? Higher VTH? Not drive as strongly Id,sat (Vgs-VTH)2 Performance? Penn ESE370 Fall2012 -- DeHon

Impact Performance Vth  Ids  Delay (Ron * Cload) Penn ESE370 Fall2012 -- DeHon

Impact of Vth Variation Think NMOS Vgs = Vdd Penn ESE370 Fall2012 -- DeHon

FPGA Logic Variation Altera Cyclone-II Xilinx Virtex 5 65nm 90nm [Tuan et al. / ISQED 2010] [Wong, FPT2007] Penn ESE370 Fall2012 -- DeHon

Impact of Vth Variation? Lower VTH? Not turn off as well  leaks more Penn ESE370 Fall2012 -- DeHon

2004 Borkar (Intel) Micro 37 (2004) Penn ESE370 Fall2012 -- DeHon

Operation Temperature Voltage Penn ESE370 Fall2012 -- DeHon

Temperature Changes Different ambient environments January in Maine July in Philly Air conditioned machine room Self heat from activity of chip Quality of heat sink (attachment thereof) Penn ESE370 Fall2012 -- DeHon

Self Heating Borkar (Intel) Micro 37 (2004) Penn ESE370 Fall2012 -- DeHon

Thermal Profile for Processor [Reda/IEEE Tr Emerging CAS v1n2 2011] Penn ESE370 Fall2012 -- DeHon

Temperature (on current?) High temperature More free thermal energy Easier to conduct Lowers Vth Increase rate of collision Lower saturation velocity Lower saturation voltage Lower peak Ids  slows down One reason don’t want chips to run hot Penn ESE370 Fall2012 -- DeHon

Temperature and Ids Penn ESE370 Fall2012 -- DeHon

Temperature (leakage?) High temperature Lowers Vth Penn ESE370 Fall2012 -- DeHon

Voltage Power supply isn’t perfect Differs from design to design Board to board? How precise is regulator? IR-drop in distribution Bounce with current spikes Penn ESE370 Fall2012 -- DeHon

Aging Hot Carrier NBTI Penn ESE370 Fall2012 -- DeHon

Hot Carriers Trap electrons in oxide Also shifts Vth Penn ESE370 Fall2012 -- DeHon

NBTI Negative Bias Temperature Instability Interface traps, Holes Long-term negative gate-source voltage Affects PFET most Increase Vth Partially recoverable? Temperature dependent Another reason not to run hot. [Stott, FPGA2010] Penn ESE370 Fall2012 -- DeHon

Measured Accelerated Aging (Cyclone III, 65nm FPGA) [Stott, FPGA2010] Penn ESE370 Fall2012 -- DeHon

Coping with Variation Penn ESE370 Fall2012 -- DeHon

Variation See a range of parameters L: Lmin – Lmax Vth: Vth,min – Vth,max Penn ESE370 Fall2012 -- DeHon

Impact of Vth Variation Higher VTH Not drive as strongly Id,sat (Vgs-VTH)2 Lower VTH Not turn off as well  leaks more Penn ESE370 Fall2012 -- DeHon

Variation Ion,min=Ion(Vth,max) Margin for expected variation Must assume Vth can be any value in range Speed  assume Vth slowest value Ion,min=Ion(Vth,max) Id,sat (Vgs-Vth)2 Probability Distribution VTH Penn ESE370 Fall2012 -- DeHon

Gaussian Distribution From: http://en.wikipedia.org/wiki/File:Standard_deviation_diagram.svg Penn ESE370 Fall2012 -- DeHon

Impact Given What maximum Vth should expect to see for a circuit of Vth,nom = 250mV Sigma 25mV What maximum Vth should expect to see for a circuit of 100 transistors? 1000 transistors? 109 transistors? Penn ESE370 Fall2012 -- DeHon

Class ended here Penn ESE370 Fall2012 -- DeHon

Variation See a range of parameters Validate design at extremes L: Lmin – Lmax Vth: Vth,min – Vth,max Validate design at extremes Work for both Vth,min and Vth,max ? Design for worst-case scenario Penn ESE370 Fall2012 -- DeHon

Margining Also margin for Temperature Voltage Aging: end-of-life Penn ESE370 Fall2012 -- DeHon

Process Corners Many effects independent Many parameters With N parameters, Look only at extreme ends (low, high) How many cases? Try to identify the {worst,best} set of parameters Slow corner of design space, fast corner Use corners to bracket behavior Penn ESE370 Fall2012 -- DeHon

Simple Corner Example What happens at various corners? 350mV Vthp Vthn Penn ESE370 Fall2012 -- DeHon

Process Corners Many effects independent Many parameters Try to identify the {worst,best} set of parameters E.g. Lump together things that make slow Vthn, Vthp, temperature, Voltage Try to reduce number of unique corners Slow corner of design space Use corners to bracket behavior Penn ESE370 Fall2012 -- DeHon

Range of Behavior Still get range of performances Any way to exploit the fact some are faster? Probability Distribution Delay Penn ESE370 Fall2012 -- DeHon

Speed Binning Sell Sell cheap nominal Discard Sell Premium Probability Distribution Delay Penn ESE370 Fall2012 -- DeHon

Midterm 1 Contents should not be a surprise Identify CMOS/non-CMOS Identify CMOS function Any logic function  CMOS gate Noise Margins Transistor Equations All regions and identify operating regions variation Circuit quasistatic configuration and switching delay Penn ESE370 Fall2012 -- DeHon

Admin HW4 First midterm next Monday Previous midterm Review on Sunday Solutions linked to 2011 syllabus Solutions linked to 2010 syllabus But only one midterm in 2010 so parts more advanced than where we are now Review on Sunday Time? Penn ESE370 Fall2012 -- DeHon

Idea Parameters Approximate Differ Robust design accommodates Chip-to-chip, transistor-to-transistor, over time Robust design accommodates Tolerance and Margins Doesn’t depend on precise behavior Penn ESE370 Fall2012 -- DeHon