Device Structure & Simulation Impact of Gate underlap on Analog & RF performance of SOI MOSFET 1Anshumaan Dash, 2Subir Kr. Maity School of Electronics Engineering KIIT University, Bhubaneswar-751024, Odisha, India 1anshumaan.dash@gmail.com,2skmaityfet@kiit.ac.in Introduction Higher transconductance generation factor and smaller output resistance and higher intrinsic gain. Variation in gm/Id, rout & intrinsic gain are shown in Fig. 4,5 and 6 respectively. Device scaling has been successfully applied over many CMOS technology generations, resulting a consistent improvement in both device density and performance. However new challenges are encountered in the scaling of conventional MOS structure much below 100nm. High channel doping concentration is required to suppress SCEs results in mobility degradation and junction leakages. Ultra thin body silicon on insulator (UTB-SOI) structure is a promising candidate that suppresses SCEs without heavily doped channel thus avoids threshold voltage variations due to random dopant fluctuations[1]. Also reduced parasitic capacitances makes it suitable for RF applications. In order to obtain further improvement in analog and RF performance with reduced SCEs , gate underlap structure exhibit its potential[2]. Moreover a higher speed and lower power dissipation can be achieved due to significant reduction of parasitic capacitances of underlap devices. In this work a simulation based investigation of analog and RF performance of gate underlap SOI MOS transistor for different underlap length is presented. Fig.04: gm/Id vs. Gate voltage Fig.05: Output Resistance vs. Gate voltage RF Performance Device Structure & Simulation The cut-off frequency (fT) and max. oscillation frequency(fMax) are two important parameters for evaluating RF FOMs. Cut-off frequency is the frequency where short circuit current gain become unity and at max. oscillation frequency All device parameters are taken according to ITRS specifications[3]. Device structure of gate underlap SOI MOS transistor is shown in Fig.1. The device under considerations includes channel doping of 1017 cm-3 with Lg of 15nm, EOT of 1.2nm, source/drain length of 5nm each, channel thickness of 3nm and BOX thickness of 15nm. Highly doped abrupt source/drain junctions are considered in this structure. Fig.06: Intrinsic gain vs. Gate voltage power gain becomes unity. Fig 7 and 8 shows variation in fT and fMax with gate bias. Due to reduction in gate capacitance device with larger underlap length exhibit superior RF performance. The supply bias is fixed at Vdd=0.8 V. To study the analog & RF performance of under lapped SOI MOSFET the simulation is performed with a drain to source voltage of 0.4 V and a variable gate to source voltage. For RF analysis input frequency varies from 0 to 100GHz. All simulations are performed by using a 2-D device simulator Sentaurus device[4]. Drift diffusion transport model with high field saturation model [5] is used to capture velocity saturation effect. Density gradient model is incorporated to consider quantum confinement. effect Fig.07: Cut-off frequency vs. Gate voltage Fig.08: Max. oscillation frequency vs. Gate voltage Fig. 01: Device structure of under lapped SOI MOS Transistor Conclusions Analog Performance Analog & RF performance of under lapped SOI MOS transistor are investigated with the help of one 2-D device simulator. Significant variations in analog & RF FOMs was observed while changing underlap length from 0 to 4nm. It was observed that when underlap length increases up to some threshold point, there is some improvement in RF FOMs. Also a trade off between analog & RF performance was observed which can be controlled by proper selection of underlap length. Analog performance of a device described by analog FOMs such as gm,gm/Id, rout and intrinsic gain(gm.rout). Fig 2 shows the drain current vs. gate voltage characteristics of under lapped SOI MOS transistor. A reduction in drain current was observed in device with increased underlap length. Fig 3 shows the transconductance variation with gate bias. Device with no underlap structure exhibit higher gm value. Device with smaller underlap length experiences higher vertical field[6] resulting a higher electron velocity and in turn in resulting a higher gm. Device with smaller underlap shows Bibliography [1] H.-S. Wong and Y. Taur, “Three-dimensional ‘atomistic’ simulation of discrete microscopic random dopant distributions effects in sub-0.1umMOSFET's,” in IEDM Tech. Dig., 1993, pp. 705–708. [2] Xuan Y, Wu, Y.Q, “High performance inversion type enhancement mode InGaAs MOSFET with max drain current exceeding 1A/mm”, Elect. Dev Lett. Vol.29, No.4 2008, pp.294-296. [3] International Technology Roadmaps for Semiconductor, ITRS, London, U.K., 2013 ed., 2013. [4] Sentaurus TCAD Manuals, Synopsys Inc., Mountain View, CA, 2013 [5] C. Canali, G. Magni, R. Minder, G. Ottaviani,” Electron and hole drift velocity measurements in silicon and their empirical relation to electric field and temperature,” IEEE Trans. Electron Devices, vol.22, no. 11, pp. 1045–1047, Nov.1975. [6] S. Russo, A. Di Carlo, IEEE Trans. Elec. Dev. 54 (2007) 1071–1075. Fig.03: Transconductance vs. Gate voltage Fig.02: Drain current vs. Gate voltage(log scale)