SoCET – System On Chip Extension Technologies Members: Travis Garza, Kuo Tian, David Castley, Siddhant Ekale, Mingxuan He Advisors: Dr. Mark Johnson, Dr. Matthew Swabey A System on chip(SoC) combines the required electronic circuits of various computer components onto a single, integrated chip (IC).  Goal: Design, test, and verify a Purdue Original System on a Chip using an iterative approach.  Currently testing/designing version x04 and verifying version x03. hardware Core (PLIC & SPI)Core (plic & spi) core Platform level Interrupt Controller (PLIC) Semester Goals: Design a Platform Level Interrupt Controller for the RISC-V core that the team has successfully simulated. Design the bridge interface from AHB to APB for successfully reading memory mapped registers used by the PLIC Core. Impedance testing between ground and power Load the python debugger using the test bed created Semester Goals To test the impedance to ensure that there was a high impedance between ground and Vcc, and a low impedance between common ground pins and common Vcc pins. To create a test bed to flash the chips using the python debugger.  Verificationverification Softwaresoftware 1) Write and maintain scripts to generate register definition header files for software testing. 2) Driver modules for the different interfaces on the chip. (Involved Writing ‘C’ code) 3) Toggle different pins for interfaces and test inputs with expected output values. Serial Peripheral Interface Semester Goals:  Design an interrupt driven only general purpose SPI Allow CPU to transmit and receive byte stream from other device   UVM Verification Semester Goals: Complete a functional verification environment using the Universal Verification Methodology Integrate a single module from x03 into the UVM framework and correctly verify functionality Core (NVM Controller)Core (nvm Controller)  Semester Goals Design a Non Volatile Memory controller for flash memory. Finalize the design diagrams  and documentation.