3DIC Consortium Meeting Multi Project Run #2 R. Yarema Fermilab Marseille, France 3DIC Consortium Meeting March 18-19, 2010

3DIC Consortium Meeting MPW Run #2 This presentation is short and primarily intended to be an open discussion about the future. 3DIC Consortium Meeting

3DIC Consortium Meeting Consortium Size The University of Sherbrooke in Canada has joined our consortium. Sherbrooke will be represented by Jean-Francois Pratte. We are pleased to welcome this new member. Our consortium now has 16 member institutions from 6 countries 3DIC Consortium Meeting

New Options Developing Discussions are ongoing with Tezzaron MOSIS CMC CMP Not available yet, but could be in the near future 3DIC Consortium Meeting

3DIC Consortium Meeting Consortium MPW Run #2 Establish options for run Number of metal layers Type of MiM capacitors Hi-Res Poly for resistors Other?? Decide on single mask set or two mask sets. Decision hinges to a large extent on the size of the biggest chips If one chip is larger than one half of the reticule size, two sets of masks are necessary If the largest chip is less than one half of the reticule size, two sets of masks may be desirable if the total area of the top tier chips exceeds one half of the reticule area. If the total area of the top tiers approaches the area of the reticule, two sets of masks is most likely the best approach. If the total of the top tier design area is less than one half the reticule size, a single mask set is the best solution unless a large quantity of chips is desired. 3DIC Consortium Meeting

EOI for Space on MPW Run #2 ATLAS - 20 x 19 mm FNAL – 10 x 10 mm IPHC-IRFU/Saclay 5 x 5 mm INFN – six locations, 5 x 5 mm Sherbrooke - 4 x 5 mm Total design area = 725 mm2 Frame useage = 725/780 = 93% 3DIC Consortium Meeting

3DIC Consortium Meeting Cost Estimate Costs based on previous MPW run (changes and additional costs possible) Mask sets - $195K x 2 = 390,000 Wafer fab - $2525/wafer x 12 x 2 = 60,000 Assembly - $2500/wafer x 12 = 30,000 Total = $480K Cost/mm2 = $480K/725 mm2 = $662/mm2 Assume $700/mm2 for a 3D stack with 2 tiers (actually only $350/ mm2 of silicon.) Die size costs 20 x 19 mm2 => $266K 10 x 10 mm2 => $70K Each 5 x 5 mm2 chip => $17.5K 5 x 4 mm2 => $14K Number of parts before yield considerations = 336/design 3DIC Consortium Meeting

3DIC Consortium Meeting Next Steps Preliminary evaluation of run #1 Confirm current space allocation or make request for additional space. Verify frame street sizes for vendor PCMs before finalizing design sizes Compile comments for next run. (What can we do better?) Provide updated design procedures and design kits from Tezzaron to the consortium. - June 2010?? Set tentative date for next submission Dec 1, 2010?? We have gained a great deal of experience which will help us in future submissions. Plan on meeting at one of the consortium institutions for presentation of test results, July, September? 3DIC Consortium Meeting

3DIC Consortium Meeting Chip Scale Review (Feb 2010) 3D Integration: Talking About a Revolution The 3D Architectures for Semiconductor Integration and Packaging conference in December reviewed progress in all areas of 3D integration and discussed different approaches. The discussions often centered on whether 3D will be implemented through small changes or large changes .i.e. evolution or revolution. It’s still an open question. It goes with out saying that 3D is still in its early stages and we have experienced first hand some of the bumps in the road. CSR - “There is no question: everyone in the industry agrees that future growth relies on the success of 3D integration, and that through silicon vias (TSVs) are the only way to achieve the required functional density at desired cost”. CSR concludes by saying “…the best way to overcome the remaining limitations (design, test, thermal management) is to take a forward-thinking approach. It’s time to take off the 2D blinders and don the 3D glasses instead.” 3DIC Consortium Meeting

3DIC Consortium Meeting So we have!! 3DIC Consortium Meeting