ADPCM Adaptive Differential Pulse Code Modulation Team M4 Andrew Akindele Edward Shim James Lee Anthony Xu Project Objectives Stage 6 Simulations Design and implement an Adaptive DPCM Manager : Joe Bakker Date Feb. 24, 2003 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Project Status Done Cadence Schematic Verilog Code Gate Level Layout Functional Block Layout (85%) Functional Block Simulations (85%) Next CLA LVS Component Corrections Chip Wiring Simulations and Verification 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Design Decisions Macroblocks for adders and muxes Helps as an intermediate step in LVS Allows some wiring of close modules Layout of CLA is taking a lot longer than expected, use RCA as backup 18-525 Integrated Circuit Design Project

Component Simulations Fall Rise ROMindex 1.43ns 0.45ns ROMstep 4.09ns 2.56ns RCA 8bit 0.54ns 1.01ns FSM FGOOD = 250Mhz Clamp_index 1.61ns 1.84ns Register FMAX=357Mhz FBAD=385Mhz 18-525 Integrated Circuit Design Project

Parasitics Used in Simulation Estimated 1fF for each nmos + pmos pair that a line drives Minimum sized inverter buffer for all inputs 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Rollercoaster Ride X 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project FSM Good 18-525 Integrated Circuit Design Project

Clamp_index Critical Path 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Clamp_index Rise 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Clamp_index Fall 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project ROMindex Fall 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project ROMindex Rise 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project ROMstep Fall 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project ROMstep Rise 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project RCA 8bit Fall 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project RCA 8bit Rise 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Register Good 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Register Bad 18-525 Integrated Circuit Design Project

18-525 Integrated Circuit Design Project Questions? 18-525 Integrated Circuit Design Project