Lecture 8 Dr. Nermi Hamza

Combinational outputs Introduction A sequential circuit consists of a feedback path, and employs some memory elements. Combinational logic Memory elements Combinational outputs Memory outputs External inputs Sequential circuit = Combinational logic + Memory Elements

Introduction There are two types of sequential circuits: synchronous: outputs change only at specific time asynchronous: outputs change at any time Bistable logic devices: latches and flip-flops. Latches and flip-flops differ in the method used for changing their state.

Memory Elements Memory element: a device which can remember value indefinitely, or change value on command from its inputs. Characteristic table: command Memory element stored value Q Q(t): current state Q(t+1) or Q+: next state

Memory Elements Memory element with clock. Flip-flops are memory elements that change state on clock signals. Clock is usually a square wave. command Memory element stored value Q clock Positive edges Negative edges Positive pulses

Memory Elements Two types of triggering/activation: Pulse-triggered edge-triggered Pulse-triggered latches ON = 1, OFF = 0 Edge-triggered flip-flops positive edge-triggered (ON = from 0 to 1; OFF = other time) negative edge-triggered (ON = from 1 to 0; OFF = other time) CS1104-11 Memory Elements

S-R Latch Complementary outputs: Q and Q'. When Q is HIGH, the latch is in SET state. When Q is LOW, the latch is in RESET state. For S-R latch (also known as NOR gate latch), R=HIGH (and S=LOW) a RESET state S=HIGH (and R=LOW) a SET state both inputs LOW a no change both inputs HIGH a Q and Q' both LOW (invalid)! CS1104-11 S-R Latch

S-R Latch Characteristics table for active-high input S-R latch: S R Q

S-R Latch S-R latch 1 1 1 1 1 R S Q Q' CS1104-11 S-R Latch

Back to the bistable element cross-coupled inverter maintains a zero or one, but has no provision for forcing a change enter the set-reset (S-R) latch cross-coupled NOR gates (control = 0) ==> inverter (control = 1) ==> zero out

The SR latch WITH Nor S R Action 0 0 Keep state 0 1 Q = 0 1 0 Q = 1 1 1 Undefined Q Q R

SR LATCH WITH NAND

Gated S-R Latch S-R latch + enable input (EN) and 2 NAND gates  gated S-R latch. CS1104-11 Gated S-R Latch

Gated S-R Latch Outputs change (if necessary) only when EN is HIGH. Under what condition does the invalid state occur? Characteristic table: EN=1 Q(t+1) = S + R'.Q S.R = 0

An SR latch with a control input Here is an SR latch with a control input C. Notice the hierarchical design! The dotted blue box is the S’R’ latch. The additional NAND gates are simply used to generate the correct inputs for the S’R’ latch. The control input acts just like an enable. October 15, 2003 Flip-flops

D latch Finally, a D latch is based on an S’R’ latch. The additional gates generate the S’ and R’ signals, based on inputs D (“data”) and C (“control”). When C = 0, S’ and R’ are both 1, so the state Q does not change. When C = 1, the latch output Q will equal the input D. No more messing with one input for set and another input for reset! Also, this latch has no “bad” input combinations to avoid. Any of the four possible assignments to C and D are valid.

D latch

Latch Circuits: Not Suitable Latch circuits are not suitable in synchronous logic circuits. When the enable signal is active, the excitation inputs are gated directly to the output Q. Thus, any change in the excitation input immediately causes a change in the latch output. The problem is solved by using a special timing control signal called a clock to restrict the times at which the states of the memory elements may change. This leads us to the edge-triggered memory elements called flip-flops.

Clocked D Flip-Flop

Flip-flops Flip-flops: bistable devices Output changes state at a specified point on a triggering input called the clock. Change state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock signal. Positive edges Negative edges Clock signal

D Flip-Flop master slave

D flip-flops when C=0 The D flip-flop’s control input C enables either the D latch or the SR latch, but not both. When C = 0: The master latch is enabled, and it monitors the flip-flop input D. Whenever D changes, the master’s output changes too. The slave is disabled, so the D latch output has no effect on it. Thus, the slave just maintains the flip-flop’s current state. October 15, 2003 Flip-flops

D flip-flops when C=1 As soon as C becomes 1, The master is disabled. Its output will be the last D input value seen just before C became 1. Any subsequent changes to the D input while C = 1 have no effect on the master latch, which is now disabled. The slave latch is enabled. Its state changes to reflect the master’s output, which again is the D input value from right when C became 1. October 15, 2003 Flip-flops

Master-Slave Edge-Triggered Flip-Flop Can connect two level-sensitive latches in Master-Slave configuration to form edge-triggered flip-flop Master latch “catches” value of “D” at “QM” when CLK is low Slave latch causes “Q” to change only at rising edge of CLK QM Master Latch Slave Latch D Q CLK 2 x 8 = 16 Transistors CLK CLK D QM Q

Jk flip-flop D = JQ' + K'Q.

Pulse transition detector T Flip-flop T flip-flop: single-input version of the J-K flip flop, formed by tying both inputs together. Characteristic table. T Q Q' CLK Pulse transition detector J C K Q Q' CLK T Q(t+1) = T.Q' + T'.Q CS1104-11 T Flip-flop

Characteristic equations We can also write characteristic equations, where the next state Q(t+1) is defined in terms of the current state Q(t) and inputs. Q(t+1) = D Q(t+1) = K’Q(t) + JQ’(t) Q(t+1) = T’Q(t) + TQ’(t) = T  Q(t) October 15, 2003 Flip-flops

At D Flip-Flop timing diagram

JD flip flop timing diagram

JD FLIP-FLOP

T flip-flop timing diagram

Shift register