3Boston University ECE Dept.; Cross-layer Floorplan Optimization for Silicon Photonic NoCs in Many-core Systems Ayse K. Coskun3, Anjun Gu1, Warren Jin4, Ajay Joshi3, Andrew B. Kahng1,2, Jonathan Klamkin4, Yenai Ma3, John Recchio1, Vaishnav Srinivas1 and Tiansheng Zhang3 UCSD 1ECE and 2CSE Dept.; 3Boston University ECE Dept.; 4UCSB ECE Dept. This research has been partially funded by the NSF grants CNS-1149703 and CCF-1149549. Work at UCSD has been supported by NSF, Samsung and the IMPACT+ Center.

Manycore Systems Integrate many simple cores for massive throughput (Thread-level parallelism) Tilera Gx Kalray MPPA-256 NoC requirements of manycore systems Long global links Large available bandwidth Low energy consumption Silicon Photonic Network

Silicon Photonic Network Silicon-photonic link Ring resonators are highly thermally sensitive Large on-chip temperature variations Localized thermal tuning λ Ring mod. λ1 Ring filter

Silicon Photonic Network Silicon-photonic link Ring resonators are highly thermally sensitive Large on-chip temperature variations Localized thermal tuning λ Ring mod. λ1 Ring filter micro-heater  Tuning power overhead

Silicon Photonic Network Silicon-photonic link Ring resonators are highly thermally sensitive Large on-chip temperature variations Localized thermal tuning λ  Tuning power overhead Laser source power consumption is large High optical loss (propagation, crossing, etc.) Low laser source efficiency Place and route (P & R) silicon photonic links to reduce optical loss

Contributions We formulate a mixed integer linear programming (MILP) based optimizer that finds P & R solutions for Clos PNoC that minimize power consumption and area combination We develop a PNoC floorplan optimization flow that is aware of on-chip thermal variations based on various power profiles We propose the notion of power weight to model core thermal impact on router element, enabling optimization with heterogeneous cores or power profiles

Outline Previous Work Cross-layer Floorplan Optimization for PNoCs Experimental Results Conclusions

Related Work Studies on Placement of Optical Devices PNoC placement’s influence on Signal to Noise Ratio [Li et al., 2015] Laser source placement’s impact on PNoC power [Chen et al., 2014] P & R Solutions for PNoC PROTON: An automatic tool for PNoC P & R [Boos et al., 2013] GLOW: A ILP based global router for PNoC [Ding et al., 2012] Optical Waveguide Routing Algorithms Reduce optical loss under a fixed netlist [Condrat et al., 2008] [Ding et al., 2009] [Ramini et al., 2013]

Floorplan Optimization Flow INPUT OUTPUT MILP-Based Optimizer Design Options & Constraints (# of cores, aspect ratios, etc.) Floorplan with Minimized PNoC Power & Area Cost Compact Thermal Model Optimization Goal: PNoC Power: P & R’s impact on waveguide length, crossing and bending Laser source efficiency PNoC placement’s impact on thermal tuning power PNoC Area: Area cost of router groups and waveguides

Floorplan Optimization Flow [# of cores, core parameters, aspect ratio (AR)]

Floorplan Optimization Notations System is formed by tiles L2 C+L1 Processor Tile with 4 Cores

Floorplan Optimization Notations Cluster (Hori.) System is formed by tiles PNoC is represented by clusters of tiles, Cluster (Vert.) L2 C+L1 Processor Tile with 4 Cores

Floorplan Optimization Notations Cluster (Hori.) System is formed by tiles PNoC is represented by clusters of tiles, location of router groups (set C), C=0 Cluster (Vert.) C=1 C=7 L2 C+L1 Processor Tile with 4 Cores

Floorplan Optimization Notations Cluster (Hori.) System is formed by tiles PNoC is represented by clusters of tiles, location of router groups (set C), and the waveguides (set N) C=0 Cluster (Vert.) Net n=0 C=1 C=7 L2 C+L1 Processor Tile with 4 Cores

Floorplan Optimization Notations Cluster (Hori.) System is formed by tiles PNoC is represented by clusters of tiles, location of router groups (set C), and the waveguides (set N) Vertex set V: potential places for router groups Edge set A: potential places for waveguides C=0 Cluster (Vert.) Net n=0 C=1 C=7 Edge Vertex L2 C+L1 Processor Tile with 4 Cores

Floorplan Optimization Flow INPUT OUTPUT MILP-Based Optimizer Design Options & Constraints (# of cores, aspect ratios, etc.) Floorplan with Minimized PNoC Power & Area Cost Compact Thermal Model Compact thermal model Accumulated thermal weight profiles Power profile: Resonant frequency difference among router groups Thermal tuning power Compact Thermal Model Size: 1×N N×M 1×M

Floorplan Optimization Flow INPUT OUTPUT MILP-Based Optimizer Design Options & Constraints (# of cores, aspect ratios, etc.) Floorplan with Minimized PNoC Power & Area Cost Compact Thermal Model Compact thermal model

Floorplan Optimization Formulation Router group related constraints Tile and cluster related constraints Path related constraints

Floorplan Optimization Formulation Only one vertex and one orientation is chosen for each router group

Floorplan Optimization Formulation Row/column index of router group c

Floorplan Optimization Formulation Orientation of the cluster of ring group c

Floorplan Optimization Formulation Shows which tiles are occupied by which cluster

Floorplan Optimization Formulation No tile can belong to more than one cluster

Floorplan Optimization Formulation A path of routing graph edges for each net n from its source sn to its sink tn

Outline Previous Work Cross-layer Floorplan Optimization for PNoCs Experimental Results Conclusions

Design of Experiments Experimental Methodology Software: ILOG CPLEX v12.5.1 Platform: 2.8GHz Xeon server Configuration Parameters: # of cores (64, 128, and 256) Network configuration (8-ary Clos) Cluster aspect ratio (1:2, 1:4, and 1:8) Chip aspect ratio (1:1, 1:2, 1:4) Optical data rate (2Gbps, 4Gbps and 8Gbps) # of waveguides (32, 64 and 128) Power Profiles: (W) Uniform Chessboard Centric Cornered Clustered Pringle

Results For different core counts: For different chip aspect ratios: Accumulated thermal weight profiles PNoC Power (W) Optimized PNoC layouts For different chip aspect ratios: Accumulated thermal weight profiles PNoC Power (W) Optimized PNoC layouts

Results For various laser source wall plug efficiency (WPE) and power profiles: Power profiles Accumulated thermal weight profiles Optimized PNoC layouts WPE: 5% WPE: 15% Chessboard 15% power saving comp. to vertical U-shape layout Clustered Pringle

Results For various optical data rate: Accumulated thermal weight profiles PNoC Power (W) Optimized PNoC layouts For different cluster power weight: High-power Cluster Low-power Cluster

Take-away Points Thermal tuning power and laser power play important roles in PNoC P & R Larger chips present an economy of scale for the PNoC power due to the more symmetric thermal weight profiles Skewed chip aspect ratios create asymmetry in the thermal weight profiles The maximum achievable optical data rate is always preferred It is important to consider different power profiles during design time

Conclusions Proposed a cross-layer, thermally- aware optimizer for floorplanning of PNoCs The optimizer minimizes PNoC power using an MILP formation through placing and routing on- chip photonic devices Compared to thermally-agnostic solutions, the proposed optimizer saves up to 15% PNoC power