RadLab PHENIX Meeting Feb.18 2014

OVERVIEW FVTX detector Requirement of FVTX trigger Setup at RIKEN Timing Measurement Analysis

FVTX(Forward Vertex) Detector p p ・20-40cm from IP ・4 layers / direction ・~1,080,000 silicon strips ・Resolution ~100um

Discrimination of Particles FVTX Each muon has each DCA(Distance of Closest Approach) depending on the parent particle → Parent particles are distinguishable by measuring DCA Trajectory Hit Point DCA Heavy quarks(c,b) are generated in proton mostly by gluons → Heavy mesons(D,B) are usable as the probe of gluon

Measurement of Low x Region Past Measurement Valence Quarks Existence Probability The measurement at low x region, where the distribution of gluon is dominant, is done by FVTX Gluons Bjorken x

Trigger Logic Trigger Hit pattern Reject Hit pattern Collision Point Hit pattern Trigger Look Up Table ・ Trigger will be generated after matching MuTr trigger, which is designed for W

Readout Devices for FVTX Silicon Strip Sensor FPHX chip Read Out Card(ROC) Front End Module(FEM) FEM Interface Board(FEMIB) BCLK distribution card(BCO) DAQ PC Processing Operation, DAQ

Readout Devices for FVTX Used for… ・Buffering data ・Combining data ・Receiving LVL1 trigger chip ID, Channel ID, ADC, Time Stamp… Trigger will be implemented on FVTX by changing the process in FPGA

Setup at RIKEN TB BCO FEMIB FPHX chip Sensor ROC FEM DATA DATA

To take much time in signal processing, Trigger can’t be in time!! PHENIX Online System Read Out Circuit ① ROC FEM ⑤ Wedge ② To take much time in signal processing, Trigger can’t be in time!! Upon developing FVTX Trigger Circuit, processing time in FVTX Trigger circuit is interesting. Trigger Circuit ④ ③ PHENIX Online System Other Detectors 読み出し回路中の処理をデザインすることで実現。FPGAを利用。FPGAとは内部処理をデザインできるハードウエア。 enable to measure processing time on FVTX Trigger circuit by measuring time until signal come in FVTX Trigger circuit ① ② ③ Measurement region Processing rime

PHENIX Online System ① ROC FEM ② Read Out Circuit ① ROC FEM Wedge ② LL1 makes trigger decision 20 BCLKs after the collision The process in LL1 consumes 3 BCLKs → The processing time between sensor and signal division point needs to be shorter than 17BCLKs (~ 1.7us) Trigger Circuit ④ ③ PHENIX Online System Other Detectors 読み出し回路中の処理をデザインすることで実現。FPGAを利用。FPGAとは内部処理をデザインできるハードウエア。 ① ② ③ ④ Measurement region Processing rime 17 BLKs 3 BLKs 20 BLKs

Timing Measurement with Calibration Pulse ・ FVTX data processing system, pulser is used on ROC for calibration ・At first, we measure processing time on trigger circuit with pulser. Observe Δt Wedge ROC FEM Sensor Readout Readout Trigger Pulser Trigger FPHX Pulser Simple trigger circuit and 13 BCO delay

Implementation of Multiplicity trigger Multiplicity trigger implement on FEM FPGA. Multiplicity Trigger 106ns = 1BCLK Each mode is selectable by changing FPGA code Trigger Signal is observable from header pin on FEM ・When there are hits on wedge and hits are larger than Min_Hits, Multiplicity Trigger sends trigger signal per wedge. ・ Multiplicity Trigger take combination between wedges (AND/OR) ・Min_Hits = 1, all OR mode.

Timing measurement with Calibration Pulse Read Out Circuit ① ROC FEM Wedge ② Trigger Circuit 28 BCLKs ③ LL1 Trigger System 13 BCLKs 15BCLKs delay 読み出し回路中の処理をデザインすることで実現。FPGAを利用。FPGAとは内部処理をデザインできるハードウエア。 ① ② ③ ・Expected requiring time for trigger processing is larger than1.5 BCLKs. ・ Result of measurement satisfy a borderline. ・However timing measurement with wedge is needed for more accurately measurement 15 BLKs 2BLKs 17 BLKs

Setup of wedge ROC FEM Readout Readout Trigger Pulser DAQ PC Sensor ROC FEM Readout Readout Trigger Pulser FPHX DAQ PC Send Trigger Per 1000 BCLKs ・To measure processing time of Trigger circuit with wedge, at first We observed data signal from wedge and analyze the data to confirm whether wedge is working or not. ・Measure BackGround

Analysis result1 Histgram of hit/event Actual histgram Count Actual histgram Predicted histgram 20 40 60 80 100 120 140 160 180 200 220 600 500 400 300 200 700 100 103 Abnormal peak Hit/Event However, abnormal peak appeared. There are no source so expected hit is almost all 0.

Analysis result 2 ROC FEM Channel vs Hit(ADC=0) Predicted histgram Too many DATA!! Read Out Circuit Wedge ROC FEM Channel vs Hit(ADC=0) Hit number(log) Predicted histgram Channel = 0 ADC = 0 Actual histgram Overflow flag Channel ・Too many data were send to readout circuit so overflow occurred in data processing circuit . ・When overflow occurrs on FEM, ADC and Channel = 0 DATA are send to DAQ

Analysis result 20 40 60 80 100 120 140 160 180 200 220 600 500 400 300 200 700 100 103 ・ There are abnormal behavior however, to remove abnormal peak and overflow flag wedge seems working.

Setup of wedge with self trigger Sensor ROC FEM Readout Readout Trigger Pulser FPHX DAQ PC Self Trigger ・To analyze deeper ,we implement self trigger circuit on FEM. ・Self trigger send trigger signal and accept signal if there are hit on wedge.

Background measurement Hit count(log) vs channel Hit number(log) Prediction Count Abnormal peak Channel Channel ・Observed abnormal peak in channel 30～50. ・All chip have same peak. ・Looks like calibration pulse is working.

Analysis result ADC vs Amplitude Amplitude ・If Calibration pulse is working , there are correlation between ADC and Amplitude like left figure. ・However there were not correlation .

Summary FVTX made for measurement of gluon polarization in proton. Trigger circuit is need for measurement. Finished setup of FVTX readout system at Riken Test Bench except for the detector. Measured the available processing time in the trigger circuit with calibration pluse. →2 BCO (satisfy a borderline) Trying to setup of the detector ,however we can’t confirm data signal from the detector because of noise ->Need to detect noise source. Measure processing time with detector (future plan)

Timing Measurement with Source (future plan) Sensor ROC FEM Observe Δt Readout Readout Trigger Pulser Sensor FPHX Scintillator Scintillator

RUN13 BBC rate vs SG3