A Readout Electronics System for GEM Detectors

Slides:

Advertisements

Similar presentations

1 500cm 83cm 248cm TPC DETECTOR 88us 1MIP = 4.8 fC = 3 x10 4 e Dynamic : 30 MIP S / N = 30:1 1MIP = 4.8 fC = 3 x10 4 e Dynamic : 30 MIP S / N = 30:1 LATERAL.

Advertisements

Front-end electronics for the LPTPC  Connectors  Cables  Alice readout electronics  New developments  New ideas  Open questions Leif Jönsson Phys.

Chapter 10 Analog Integrated Circuits The 741 OP-AMP Introduction.

Electronics for large LAr TPC’s F. Pietropaolo (ICARUS Collaboration) CRYODET Workshop LNGS, March 2006.

E. Atkin, E. Malankin, V. Shumikhin NRNU MEPhI, Moscow 1.

Specific requirements for analog electronics of a high counting rate TRD Vasile Catanescu NIHAM - Bucharest CBM 10th Collaboration Meeting Sept 25 – 28,

SKIROC New generation readout chip for ECAL M. Bouchel, J. Fleury, C. de La Taille, G. Martin-Chassard, L. Raux, IN2P3/LAL Orsay J. Lecoq, G. Bohner S.

A scalable DAQ system using the DRS4 sampling chip H.Friederich 1, G.Davatz 1, U.Hartmann 2, A.Howard 1, H.Meyer 1, D.Murer 1, S.Ritt 2, N.Schlumpf 2 1.

1 Luciano Musa CERN participation to EUDET for TPC electronics CERN, 31 August 2006 Outline Part I – Development of the readout electronics for the LPTPC.

Front-end electronics for Time Projection Chamber I.Konorov Outlook:  TPC requirements  TPC readout options  Options for TPC FE chips  Prototype TPC.

HEP2005, Lisboa July 05 Roberto Campagnolo - CERN 1 HEP2005 International Europhysics Conference on High Energy Physics ( Lisboa-Portugal,

Development of novel R/O electronics for LAr detectors Max Hess Controller ADC Data Reduction Ethernet 10/100Mbit Host Detector typical block.

NA62 front end architecture and performance Jan Kaplon/Pierre Jarron.

14-5 January 2006 Luciano Musa / CERN – PH / ED General Purpose Charge Readout Chip Nikhef, 4-5 January 2006 Outline  Motivations and specifications 

Front-end electronics for the LPTPC  System lay out  End-cap and panels  Mechanics for the front-end electronics  Connectors and cables  Front-end.

 Chip v4: Measurement from room temperature down to LN2.  Chip v4: MIP signal with oscilloscope persistence  Experimental results of various versions.

Preliminary LumiCAL FEE Specification Presented by Alexander Solin NC PHEP FCAL collaboration meeting, February 12-13, 2006, Krakow (INP PAS),

1HSSPG Georgia Tech High Speed Image Acquisition System for Focal-Plane-Arrays Doctoral Dissertation Presentation by Youngjoong Joo School of Electrical.

L.Royer– Calice DESY – July 2010 Laurent ROYER, Samuel MANEN, Pascal GAY LPC Clermont-Ferrand R&D LPC Clermont-Fd dedicated to the.

21-Aug-06DoE Site Review / Harvard(1) Front End Electronics for the NOvA Neutrino Detector John Oliver Long baseline neutrino experiment Fermilab (Chicago)

25th June, 2003CMS Ecal MGPA first results1 MGPA first results testing begun 29 th May on bare die (packaging still underway) two chips looked at so far.

P. Baron CEA IRFU/SEDI/LDEFACTAR Meeting Santiago de Compostela March 11, A review of AFTER+ chip Its expected requirements At this time, AFTER+

Front-end readout study for SuperKEKB IGARASHI Youichi.

L.ROYER – TWEPP Oxford – Sept The chip Signal processing for High Granularity Calorimeter (Si-W ILC) L.Royer, J.Bonnard, S.Manen, X.Soumpholphakdy.

Hold signal Variable Gain Preamp. Variable Slow Shaper S&H Bipolar Fast Shaper 64Trigger outputs Gain correction (6 bits/channel) discriminator threshold.

Development of the Readout ASIC for Muon Chambers E. Atkin, I. Bulbalkov, A. Voronin, V. Ivanov, P. Ivanov, E. Malankin, D. Normanov, V. Samsonov, V. Shumikhin,

1 Luciano Musa, Gerd Trampitsch A General Purpose Charge Readout Chip for TPC Applications Munich, 19 October 2006 Luciano Musa Gerd Trampitsch.

L.Royer– Calice LLR – Feb Laurent Royer, J. Bonnard, S. Manen, P. Gay LPC Clermont-Ferrand R&D pole MicRhAu dedicated to High.

ASIC Activities for the PANDA GSI Peter Wieczorek.

Meeting from Mai 10th at ETHZ ArgonTube electronics Charge amplifier or linear amplifer ? Front end module Max Hess.

LC Power Distribution & Pulsing Workshop, May 2011 Super-ALTRO Demonstrator Test Results LC Power Distribution & Pulsing Workshop, May nd November.

TPC electronics Status, Plans, Needs Marcus Larwill April

HBD/TPC Electronics Status Works done to for a)Prototype detector readout b)Understand packing density and heat loading issues c)Address the overall system.

Click to edit Master subtitle style Presented By Mythreyi Nethi HINP16C.

S. Bota – Calorimeter Electronics overview - July 2002 Status of SPD electronics Very Front End Review of ASIC runs What’s new: RUN 4 and 5 Next Actions.

1 19 th January 2009 M. Mager - L. Musa Charge Readout Chip Development & System Level Considerations.

ASIC Development for Vertex Detector ’07 6/14 Y. Takubo (Tohoku university)

CBM 12 th Meeting, October 14-18, 2008, Dubna Present status of the first version of NIHAM TRD-FEE analogic CHIP Vasile Catanescu and Mihai Petrovici NIHAM.

Juin 1st 2010 Christophe Beigbeder PID meeting1 PID meeting Electronics Integration.

Flex Cable Readout unit Si Sensor 256 analog lines Interconnect board NCC signal packaging concept PA board -This is the calorimeter – all pads in the.

Overview of TPC Front-end electronics I.Konorov Outline:  TPC prototype development  Readout scheme of the final TPC detector and further developments.

Analog Circuits Hiroyuki Murakami. CONTENTS Structure of analog circuits Development of wide linear range CSA system Problem of analog circuits How to.

Status of hardware activity in CNS Taku Gunji Center for Nuclear Study University of Tokyo 1.

MADEIRA Valencia report V. Stankova, C. Lacasta, V. Linhart Ljubljana meeting February 2009.

Construction of RHIC-STAR TOF and high rating MRPC Wang Yi Department of Engineering Physics, Tsinghua University Beijing,100084, China.

The design of fast analog channels for the readout of strip detectors in the inner layers of the SuperB SVT 1 INFN Sezione di Pavia I Pavia, Italy.

“Test vehicle” in 130nm TSMC for CMS HGCAL

KLOE II Inner Tracker FEE

FEE for TPC MPD__NICA JINR

Journées VLSI-FPGA-PCB Juin 2010 Xiaochao Fang

Jinfan Chang Experimental Physics Center , IHEP Feb 18 , 2011

A General Purpose Charge Readout Chip for TPC Applications

CTA-LST meeting February 2015

Activity report of FoCAL from CNS

96-channel, 10-bit, 20 MSPS ADC board with Gb Ethernet optical output

R&D activity dedicated to the VFE of the Si-W Ecal

Power pulsing of AFTER in magnetic field

A Low Power Readout ASIC for Time Projection Chambers in 65nm CMOS

A Fast Binary Front - End using a Novel Current-Mode Technique

Status of n-XYTER read-out chain at GSI

X. Zhu1, 3, Z. Deng1, 3, A. Lan2, X. Sun2, Y. Liu1, 3, Y. Shao2

BESIII EMC electronics

SKIROC status Calice meeting – Kobe – 10/05/2007.

Turning photons into bits in the cold

Signal processing for High Granularity Calorimeter

Readout Electronics for Pixel Sensors

PID meeting Mechanical implementation Electronics architecture

Presented by T. Suomijärvi

Readout electronics system for Laser TPC prototype

Readout Electronics for Pixel Sensors

Presentation transcript:

A Readout Electronics System for GEM Detectors IEEE NPSS Real Time Conference 2009 A Readout Electronics System for GEM Detectors Zhi Deng, Yinong Liu, Guanghua Gong Dept. of Engineering Physics, Tsinghua University IHEP, Beijing, China, May 10-15,2009

GEM Detectors GEM-TPC @ Tsinghua

Architecture of Readout Electronics electrons Readout pads CASA Commercial ADC (10bit, ~10MSPS) FPGA (DSP) DAQ Detector Analog Front-ends Digital Back-ends

CASA: the Front-end ASIC CSA Gain Stage 1st Shaper 2nd Shaper Variable value of C, giving different charge gain, together with matched size of the MOS transistor A dummy shaper amplifier, transfer signals to differential A fully differential amplifier, with class-AB output stage

Specifications of CASA Input Charge 10-1500fC SNR for MIP >20:1 Gain (Differential) 1-28mV/fC, adjustable Shaping Time (t) 25-100ns, adjustable Output Swing 2 V p-p, differential Drive Load 10pF Crosstalk <1% Power Consumption <10mW/ch

Chip Performance Test Input Protection Circuits CASA in CPGA package Power: 8.9 mW/ch Crosstalk: <0.98%

Programmability Programmable gain Programmable t Adjustable baseline

Noise Performance Noise@ Different gain Noise@ Different t

Linearity

With GEM detector COOL-X X-ray Generator (peak @~8keV) GEM detector CASA and buffer chips

Sampling and DSP Board Input Buffer AD9212 CLK Xilinx XC4VSX35

Sampled Noise Spectrum Normalized Power Spectrum Density Continuous Frequency /Hz f-3dB=100M

The Impact to SNR no pre-filter tr,preamp =5ns with pre-filter

Test Results

Summary A waveform sampling readout electronics system has been developed for GEM detectors, using a front-end ASIC and commercial ADC and FPGA chips. The front-end ASIC has been tested and work successfully. The sampling and DSP board has been designed and will be tested soon. The dependence of SNR with the sampling frequency has been quantitatively studied, which is very important for control of power consumption.