K-map: Product-of-Sums Minimization Lecture Digital Systems K-map: Product-of-Sums Minimization A K-map can also be used for Product-of-Sums minimization (instead of Sum-of-Products). In this case, we group the 0s and get the minimized form of the maxterms, and then take the multiplication of them. BC A 00 01 11 10 1 (A + B’) (B’ + C) B’ AC F = πM(2,3,6) F = (A + B’)(B’ + C) F = B’ + AC

Exercise: PoS Minimization Lecture Digital Systems Exercise: PoS Minimization YZ WX 00 01 11 10 1 (W + X) (W + Z) (W’ + X’ + Y’ + Z’) FPoS = (W + X)(W + Z)(W’ + X’ + Y’ + Z’) Find FSoP for the K-map above. Compare the costs between FPoS and FSoP. ?

Exercise: SoP and PoS Minimization Lecture Digital Systems Exercise: SoP and PoS Minimization Examine the following K-maps. Which one is cheaper? The minimization result using SoP or PoS? BC A 00 01 11 10 1 BC A 00 01 11 10 1

Exercise: PoS Minimization Lecture Digital Systems Exercise: PoS Minimization Compare between the cost of SoP and PoS minimization for the function: F(A,B,C) = Σm(2,3,6). Cost = Σ gates + Σ gate inputs F = A’B + BC’ Cost = 5 + 8 = 13 (SoP Minimization) F = B(A’+C’) Cost = 4 + 6 = 10 (PoS Minimization) A

Exercise: SoP and PoS Minimization (1) Lecture Digital Systems Exercise: SoP and PoS Minimization (1) YZ AB 00 01 11 10 1 X YZ AB 00 01 11 10 1 X SoP Minimization PoS Minimization FSoP = A’Z + AB’ FPoS = (A + Z)(A’ + B’) Cost = 5 gates + 8 inputs = 13 Cost = 5 gates + 8 inputs = 13

Exercise: SoP and PoS Minimization (2) Lecture Digital Systems Exercise: SoP and PoS Minimization (2) YZ AB 00 01 11 10 1 X YZ AB 00 01 11 10 1 X SoP Minimization PoS Minimization FSoP = A’Y’Z + AB’ FPoS = (A + Z)(A’ + B’)(A + Y’) Cost = 6 gates + 10 inputs = 16 Cost = 7 gates + 12 inputs = 19

Exercise: PoS Minimization Lecture Digital Systems Exercise: PoS Minimization Perform the PoS minimization for the following function by using K-map: F(A,B,C,D) = Σm(0,2,7,8,14,15) + d(3,6,9,12,13).

Application of K-map: Full Adder Lecture Digital Systems Application of K-map: Full Adder Full Adder Cin Cout S B A A full adder is a circuit that adds three single binary digits A, B, and Cin. A and B are the operands, Cin is a bit carried in from the previous less significant stage. It has two outputs, sum (S) and carry (Cout). The carry signal represents an overflow into the next digit of a multi-digit addition. The truth table of one-bit adder is as follows: A B Cin S Cout 1 credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20. Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.

Application of K-map: Full Adder Lecture Digital Systems Application of K-map: Full Adder Full Adder Cin Cout S B A Using sum of product, Cout = A’·B·Cin + A·B’·Cin + A·B·Cin’ + A·B·Cin S = A’·B’·Cin + A’·B·Cin’ + A·B’·Cin’ + A·B·Cin This function for Cout requires 8 AND Gates and 3 OR Gates (all with 2-inputs). How to simplify the circuit? A B Cin S Cout 1 credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20. Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.

Application of K-map: Full Adder Lecture Digital Systems Application of K-map: Full Adder Full Adder Cin Cout S B A K-map for Cout Cout = AB + ACin +BCin A B Cin S Cout 1 Reduction to 3 AND Gates and 2 OR Gates K-map for S credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20. Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs. S = A’B’Cin + A’BCin’ + AB’Cin’ + ABCin No possible reduction

Application of K-map: Two-bit Comparator Lecture Digital Systems Application of K-map: Two-bit Comparator A two-bit comparator compares 2 binary numbers, AB and CD. If AB < CD, then LT = 1 If AB = CD, then EQ = 1 If AB > CD, then GT = 1 We will need three 4-variable K-maps to implement this digital circuit. One map for each output. Two-bit Comparator LT B A D C EQ GT

Application of K-map: Two-bit Comparator Lecture Digital Systems Application of K-map: Two-bit Comparator K-map for LT K-map for EQ K-map for GT CD AB 00 01 11 10 1 CD AB 00 01 11 10 1 CD AB 00 01 11 10 1 LT = A’B’D + B’CD + A’C EQ = A’B’C’D’ + A’BC’D + ABCD + AB’CD’ GT = BC’D’ + ABD’ + AC’

Lecture Digital Systems Design Exercise: BCD + 5 Design a digital circuit with BCD as input, and BCD + 5 as the output. BCD + 5 I2 I1 I4 I3 O2 O1 O4 O3 I1 I2 I3 I4 O1 O2 O3 O4 1 X

Design Exercise: BCD + 5 O1 = … O2 = … O3 = … O4 = … K-map for O1 Lecture Digital Systems Design Exercise: BCD + 5 K-map for O1 K-map for O2 I3I4 I1I2 00 01 11 10 1 X I3I4 I1I2 00 01 11 10 1 X K-map for O3 K-map for O4 I3I4 I1I2 00 01 11 10 1 X I3I4 I1I2 00 01 11 10 1 X O1 = … O2 = … O3 = … O4 = …

Lecture Digital Systems Design Exercise: BCD × 3 Design a digital circuit that will multiply a BCD input by 3, and deliver the multiplication result as the output. BCD × 3 I2 I1 I4 I3 O2 O1 O4 O3 I1 I2 I3 I4 O1 O2 O3 O4 1 Fill out by yourself

Design Exercise: BCD × 3 O1 = … O2 = … O3 = … O4 = … K-map for O1 Lecture Digital Systems Design Exercise: BCD × 3 K-map for O1 K-map for O2 I3I4 I1I2 00 01 11 10 I3I4 I1I2 00 01 11 10 K-map for O3 K-map for O4 Fill out by yourself I3I4 I1I2 00 01 11 10 I3I4 I1I2 00 01 11 10 O1 = … O2 = … O3 = … O4 = …

Parity Method for Error Detection Digital Systems Section 7 Parity Method for Error Detection

Parity Method for Error Detection Lecture Digital Systems Parity Method for Error Detection The movement of binary data and codes from one location to another is the most frequent operation in digital systems. Whenever information is transmitted from one device (the transmitter) to another device (the receiver), there is a possibility that errors can occur such that the receiver does not receive the identical information as sent by the transmitter. The transmitter send a noise-free serial digital signal over a signal line to a receiver. However, by the time the signal reaches the receiver, it contains a certain degree of noise superimposed on the original signal.

Parity Method for Error Detection Lecture Digital Systems Parity Method for Error Detection If the noise is large enough in amplitude, it may alter the logic level of the signal. When this occurs, the receiver may incorrectly interpret a logic 0 as a logic 1. One of the simplest and most widely used schemes for error detection is the parity method.

Lecture Digital Systems Parity Bit A parity bit is an extra bit that is attached to a code group that is being transferred from one location to another. The parity bit is made either 0 or 1, depending on the number of 1s that are contained in the code group. Even-parity method: the value of the parity bit is chosen so that the total number of 1s in the code group (including the parity bit) is an even number. Odd-parity method: the value of the parity bit is chosen so that the total number of 1s in the code group (including the parity bit) is an odd number. credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20. Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.

Using Even-Parity Method Lecture Digital Systems Using Even-Parity Method Suppose that the code group is 1 0 0 0 0 1 1 (ASCII code for character “C”). We apply even-parity method. The code has three 1s. Therefore, we will add a parity bit of 1 to make to total number of 1s become an even number. The new code group, including the parity bit becomes: 1 1 0 0 0 0 1 1 Added parity bit If the code group is 1 0 0 0 0 0 1 (ASCII code for character “A”). The code has two 1s. Therefore, we will add a parity bit of 0 to keep to total number of 1s be an even number. The new code group, including the parity bit becomes: 0 1 0 0 0 0 0 1 credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20. Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs. Added parity bit

Lecture Digital Systems Parity Bit Attach an even-parity bit to the BCD code for decimal 69. ? A transmitter and a receiver agree to use odd-parity. A word of 1 0011 0101 is sent by the transmitter and a word of 1 1010 0101 is received by the receiver. Can the receiver detect the double error? credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20. Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs. 0 0110 1001 A No. Two errors would not change the oddness or evenness of the number of 1s in the data.

Parity Generator and Parity Checker Lecture Digital Systems Parity Generator and Parity Checker Below, one type of logic circuitry that is used for parity generation and parity checking is introduced (4 bits of data, even-parity bit). How do odd-parity generator & checker look like? ? credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20. Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.

Digital Systems Section 8 Hazards

Lecture Digital Systems Hazards Logic gates have inherent delay. They are made of electronic components which require time to process the inputs to become the output. This delay is very small (in the order of ns) and we have been ignoring this. X Y F A A’ One gate delay, A 1 A’ X One gate delay Y F 1

Lecture Digital Systems Hazards A hazard is an unwanted alternating value at the output of a combinational circuit. Hazard depend on the input patterns. A circuit can be free from hazard if the input pattern that would cause the glitch never occur. We must be aware of the possible sources of hazard and ensure that the transition in a circuit will be hazard free. The oscillating value at the output of a combinational circuit, before it settles to a certain value is referred to as glitches. We must reduce hazard because: Hazard wastes power  power consumption is proportional to number of signal transitions / switching activity. Hazard may create incorrect circuit operation  dangerous if a decision is made while output is not stable Hazard causes circuit noise  may affect other parts of the circuit.

Lecture Digital Systems Types of Hazards Static hazard: when an input variable changes its value, a signal is supposed to remain at a certain logic value, but instead the signal undergoes a momentary change. Dynamic hazard: when an input variable changes its value, a signal is supposed to change to a new logic value, but such change involves a short oscillation (glitches) before the signal settles into its new value.

Minimum cost, contain hazard Lecture Digital Systems Static Hazard The equation for the following circuit is: F = AB + B’C. A B C F BC A 00 01 11 10 1 Minimum cost, contain hazard An input change from [111] to [101] results in a static hazard. Output F will change from 1  0  1 This is due to delay of the inverter gate. Hazard happens when moving from one implicant to the other. A One gate delay B C F 1

Static Hazard: In Detail Lecture Digital Systems Static Hazard: In Detail A One gate delay B C F 1 X Y Z A B C F Y X Z

No longer minimum cost, but hazard-free Lecture Digital Systems Static Hazard When hazard occurs because two adjacent 1’s are not covered by a single implicant, then the solution is to add an extra implicant to provide the required coverage. BC A 00 01 11 10 1 Now, F = AB + B’C + AC. The circuit is no longer in minimum form with lowest cost. But now, we face no hazard anymore. A B C F No longer minimum cost, but hazard-free

Example: Removal of Static Hazard Lecture Digital Systems Example: Removal of Static Hazard Given F(A,B,C,D) = Σm(6,7,8,9,12,13,14,15). Find out situation where static hazard may occur. Find the solution.

Lecture Digital Systems Dynamic Hazard Dynamic hazard occurs only in multi-level combinational circuits. This hazard is due to paths with different length in the circuits. If the output signal changes its value three times, 0  1  0  1, the there must be at least three paths from the input to the output. A circuit that has a dynamic hazard must also have a static hazard in some part of it, where an intermediate signal changes from 0  1  0 or 1  0  1. Dynamic hazard in multi-level circuits is due to the use of factoring or decomposition techniques. We can avoid dynamic hazards simply by using two-level circuits and ensuring no static hazards.

Lecture Digital Systems Dynamic Hazard An example of dynamic hazard is below. Three paths with different lengths can be found. (Name them!) The circuit contains static hazard at b (see the timing diagram). Find the truth table of the above circuit A

Lecture Digital Systems Summary A properly designed two-level Sum-of-Product circuit has no static-0 hazards. It may have static-1 hazards. A properly designed two-level Product-of-Sum circuit has no static-1 hazards. It may have static-0 hazards. Dynamic hazards do not occur in a properly designed two-level SoP or PoS circuit. It may occur in multilevel circuits. A brute-force method of obtaining a hazard-free realization is to use the canonical SoP or canonical PoS. Hazard analysis and elimination are typically needed in the design of asynchronous sequential circuits.

Lecture Digital Systems Homework 6 (1/2) Encode the following code using even-parity method (Hint: the place for parity bit is the first bit): (i) 1011110 (ii) 110110 The following codes are received after transmission using odd- parity method. Determine whether each code is correct or error. (i) 101011011 (ii) 001110011 A multiplier circuit must deliver the multiplication result of the inputs. The inputs are two 2-bit binary numbers, x1x0 and y1y0. The output is a 4-bit binary number z3z2z1z0. Design the multiplier circuit. See next slide.

Lecture Digital Systems Homework 6 (2/2) Find a hazard-free minimum-cost PoS implementation of the function: F(A,B,C,D) = πM(0,2,3,7,10) + d(5,13,15). Please write your Class number after your Student ID. Deadline: 1 day before class. Monday, 16 October 2017 (Class 2). Tuesday, 17 October 2017 (Class 1).