14-NM TECHNOLOGY & FinFET in MICROWIND Etienne.sicard@insa-toulouse.fr

14-NM MAKES THE BREAKING NEWS Feb. 2015 - http://phandroid.com/2015/02/16/exynos-7-14nm/

1 GENERAL TRENDS

Electronic Market Growth Share of system sales 2020 vs 2015 VISION 2020 Increasing disposable income, Expanding urban population, Growing internet penetration and Availability of strong distribution network Smartphones Internet of Things PC TV Automotive Tablets Game consoles Medical Servers -10% Growth 10% 20% Electronic Market Growth

Technology 130nm 90nm 45nm 28nm 14nm 5nm Complexity 100M 250M 500M 2G This application note Technology 130nm 90nm 45nm 28nm 14nm 5nm Complexity 100M 250M 500M 2G 7G 150 G Packaging Mobile generation 3G+ 4G 4G+ 5G 3G 2004 2007 2010 2013 2016 2020 Core+ DSP 1 Mb Mem Core DSPs 10 Mb Mem Dual core Dual DSP RF Graphic Process. 100 Mb Mem Sensors Quad Core Quad DSP 3D Image Proc Crypto processor Reconf FPGA, Multi RF 1 Gb Memories Multi-sensors ? Embedded blocks

TOWARDS 10GT This application note 8-bit 10 GT in 2015 1 GT in 2010 Multi-core 16 bit 32 bit Dual core Quadcore 1 GT in 2010 This application note

FINFET This application note MOSFET ROADMAP TO 5-NM MOS FinFET for increasing drive current and reducing leakage Close to atomic scale (0.2 nm) MOS Current drive (mA/µm) High K Metal Gate to increase field effect Strain to increase mobility 2.5 FINFET High performance This application note 2.0 General Purpose MOSFET 1.5 Low power Ioff: 100nA/µm 1.0 10nA 1 nA 0.5 0.0 130 90 65 45 32 20 14 10 7 5 Technology node (nm) Intrinsic perf. Gate material Strain

SUPPLY VOLTAGE SCALE DOWN VDD is lowered to 800mV in 14-nm technology 14-nm technology Supply (V) 5.0 0.8 V inside, 1.2V outside 3.3 I/O supply 2.5 Core supply 1.8 1.2 1.0 0.35µ 0.18µ 130n 90n 65n 45n 32n 20n 14n 10n 7n Technology node

65nm 28nm 14nm Power -50% -80% 65nm 28nm 14nm SCALE DOWN BENEFITS Smaller Faster Less power consumption Cheaper (if you fabricate millions) 65nm 28nm 14nm Power -50% -80% 65nm 28nm 14nm

SCALE DOWN BENEFITS Maximum die size One Core One core AMD dual core 65nm Intel Octa core 22nm 8 cores instead of 1 using the same space 3 times faster 10 times less power consumption

REASONS OF COST EXPLOSION TECHNOLOGY INNOVATION & COST REASONS OF COST EXPLOSION Performance improvements Strain eSiGe, High-K dielectric Metal gate Low-K inter dielectrics, FinFET New options Local interconnects New constraints double patterning, FinFET

TECHNOLOGY INNOVATION & COST Less and less companies in the 14-nm market Keynote_Ajit Manocha_GLOBALFOUNDRIES

Data Rate per pin (Gb/s) CURRENT CHANGES Technology Faster and faster memory DDR4, LPDDR is on the market DDR5, LPDDR5 is under development DDR4: 250ps 2010 Laptop Memory 2012 2014 2016 2018 2020 Data Rate per pin (Gb/s) DDR3 DDR2 1 Gb/s 10 Gb/s 100 Gb/s WideIO LPDDR2 LPDDR3 DDR4 LPDDR1 Mobile Memory WideIO2 LPDDR4 DDR5 We are Here 3D 2D

Embedded SiGe (e-SiGe) Improved p mobility High K gate dielectric TECHNOLOGY INNOVATION & COST Main target Type of innovation First order effect Device performance Strain Improved n mobility Embedded SiGe (e-SiGe) Improved p mobility High K gate dielectric Increased field effect Metal gate Decreased leakage FinFET Higher current density Interconnect performance Low K inter dielectrics Reduced crosstalk and delay Local interconnect Higher density Manufacturability Double patterning Improved yield

2500 1000 design rules DESIGN RULES Microwind DRC only checks 100 basic design rules In 14-nm technology, more than 2500 design rules have been listed 130nm 500 design rules 65nm 1000 design rules 14nm 2500

ABOUT MICROWIND

www.microwind.org WHAT IS MICROWIND Microwind is an educational tool for designing nano-CMOS cells Microwind may be configured in any technology from 1.2µm downto 14nm Microwind illustrates 2D, 3D aspects of Ics Microwind simulates cells & blocks using embedded simulator www.microwind.org

Application notes on deep-sub-micron Application notes on nano-cmos PARADIGM SHIFT 2005 2010 2015 2020 Application notes on deep-sub-micron Application notes on nano-cmos Application notes on advanced topics Microwind used for research More than 100 publ/year Research started 10 publ. per year Microwind for MSc. education Microwind for B. Sc. education Links to research & developments Links to industrial projects

2nd generation strain, 10 metal layers 32/28nm 2010 High-K metal gate NANO-CMOS APPLICATION NOTES Technology node   Year of introduction Key Innovations 90nm 2003 SOI substrate 65nm 2004 Strain silicon 45nm 2008 2nd generation strain, 10 metal layers 32/28nm 2010 High-K metal gate 20nm 2013 Replacement metal gate, Double patterning, 12 metal layers 14nm 2015 FinFET www.microwind.org > Application Notes

14-NM APPLICATION NOTE Microwind’s 14-nm rule file has been tuned to the 14-nm technology information based on available publications The FinFET has been introduced in Microwind Layout, size and performances inspired from 14-nm FinFET proposed by IMEC, Belgium, Princeton University, USA, Standard cell level parasitics assessment in 20nm BPL and 14nm BFF P. Schuddinck, IEDM 2012 3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits Ajay N. Bhoj, IEEE VLSI, Vol 21, N°11, 2013

MICROWIND LAMBDA-BASED DESIGN Gate pitch Microwind works in lambda units (λ) Not optimum but independant of technology Design rules have remained nearly the same for 20 years λ is nearly half of technology (8nm in 14-nm node) Channel length is 2 λ Minimum gate pitch is 8 λ (2+6) Minimum metal pitch is 6 λ (3+3) Channel length Metal pitch

3 FINFET IMPLEMENTATION

The FinFET device has a different layout style than the MOS device FROM MOSFET TO FINFET >= 20nm <= 14nm The FinFET device has a different layout style than the MOS device Instead of a continuous channel, the FinFET uses fins FinFET provides the same Ion current at a smaller size FinFET provides lower leakage current Ioff at the same Ion fins

New screen in Microwind INTRODUCING THE FINFET MOS Parameter Typical value Width (W) 6 - 12 λ Length (L) 2 λ FinFET Parameter Typical value Number of fins (NF) 2 - 5 Fin pitch (PF) 6 λ Fin thickness (TF) 1 λ Fin length or gate length (LG) 2 λ New screen in Microwind

3D OF FINFET USING MICROWIND Microwind enables a 3D view of the FinFET P-FinFET Fin 4 Drain Fin 3 Fin length (LG) Fin 2 Fin thickness (TF) Source Fin 1 Fin height (HF) Gate N-FinFET

FIN from Drain to Source Total equivalent channel width Weq FIN BENEFITS Fin thickness (TF) The total equivalent channel width is higher in FinFET than in MOSFET Weq = 2*HF+TF Benefit around 30% in current drive Gate Fin height (HF) FIN from Drain to Source Total equivalent channel width Weq MOS Fin Ioff Patton, Evolution and Expansion of SOI in VLSI Technologies: Planar to 3D, IEEE International SOI Conference 2012 Ion

Acceptable for simulators MOS MODELS Microwind uses Level1, Level3, and a simplified version of BSIM4, adapted to FinFET “Typically, FinFET models have over 1,000 parameters per transistor, and more than 20,000 lines of C code” BSIM in Microwind uses 25 parameters and 250 lines of code… but makes many simplifications Bsim CMG Bsim6 Acceptable for simulators 1000 Bsim4 Bsim3 Bsim2 Bsim Model parameters 100 MM9 Level 2 Level 3 Acceptable for teachers 10 Level 1 Acceptable for students 1 1970 1980 1990 2000 2010 2020 Year

With 2 fins, Weff=140nm FINFET MODEL BSIM4 is a good model for MOS devices BSIM-CMG is targetted to FinFET, but corresponds to a completly new model The HFIN and TFIN parameters have been added to BSIM4 in Microwind to handle the FinFET HFIN: Fin Height TFIN: Fin thickness Fin thickness (TF) 10nm With 2 fins, Weff=140nm Fin height (HF) 30nm

GENERATING A FINFET Fin Length, equal to gate length, (LG) is 2 lambda (16 nm) by default Fin thickness (TF) is set to 1 lambda (8 nm) Fin pitch (PF) is set to 6 lambda (48nm) FinFET comme with dummy gates for manufacturability

GENERATING A FINFET HD: High density drawing style : 2 fins HP : High performance drawing style : 4 fins 1 fin exists in very high density cells such as SRAM FinFET with more than 4 fins drive string currents

4 DESIGN FOR MANUFACTURABILITY

Ion Ion Ioff Ioff FINFET MANUFACTURABILITY Fins should be aligned and horizontal, regular pitch 6  (1+5) Non-aligned fins may lead to gate distortion and current performance spread Ion Ion Ioff Ioff

FINFET MANUFACTURABILITY Gates should be aligned and vertical, regular pitch with 8  minimum (2+6)

Main target Pitch  nm Used for M7, M8 4 24 192 Supply M5, M6 3 18 144 INTERCONNECTS Metal stack Main target Pitch  nm Used for M7, M8 4 24 192 Supply M5, M6 3 18 144 Long routing M3, M4 2 12 96 Medium routing M1, M2 1.4 8 64 Short routing Gate, Local interc. 1 6 48 Intra-cell routing

5 ROADMAP TO 5NM

“ULTIMATE INTEGRATION” WAS 150-nm IN 1985 20-nm in 2000 3-nm in 2015 … ROADMAP TO 5-NM “ULTIMATE INTEGRATION” WAS 150-nm IN 1985 20-nm in 2000 3-nm in 2015 … http://www.extremetech.com

MICROWIND ROADMAP TO 5-NM Unit Code Rule 14-nm 10-nm 7-nm 5-nm Lambda λ lambda 8 6 4 3 Core supply V VDD Vdd 0.8 0.65-0.75 0.40-0.60 0.30-0.45 Fin Width WF R301 1 Fin pitch FP R308 5 Fin Height HF thdn 30 28 25 20 Gate height GH thpoly 50 45 40 35 Gate length GL R302 2 Gate pitch GP Spacer width SW 10 7 Contact size CS R401 EOT Nm b4toxe 0.9 0.85 0.80 M1 pitch R501, R502 Rule file Cmos14nm Cmos10nm Cmos7nm Cmos5nm Release 2016 2017 2018 2019

ACKNOWLEDGMENTS Kaushik Vaidyanathan, Carnegie Mellon University Mitsuhiro Togo, GlobalFoundries Pieter Schuddinck, IMEC Fumihiko Sato, IBM

Thank you for your attention Etienne.sicard@insa-toulouse.fr