TECHNOLOGY TRENDS

TOWARDS 10GT 8-bit 10 GT in 2015 1 GT in 2010 Multi-core Quadcore Dual core Quadcore 1 GT in 2010

Data Rate per pin (Gb/s) FASTER MEMORY/PROCESSOR DATA EXCHANGES Data exchange between processor and memories Needs for increased data rate DDR4: 250ps 2010 Laptop Memory 2012 2014 2016 2018 2020 Data Rate per pin (Gb/s) DDR3 DDR2 1 Gb/s 10 Gb/s 100 Gb/s WideIO LPDDR2 LPDDR3 DDR4 LPDDR1 Mobile Memory WideIO2 LPDDR4 DDR5 We are Here 3D 2D

SUPPLY VOLTAGE SCALE DOWN 7-nm technology 5.0 3.3 0.65 V inside, 1.0 V outside I/O supply 2.5 Core supply 1.8 1.2 1.0 0.35µ 0.18µ 130n 90n 65n 45n 32n 20n 14n 10n 7n Technology node

Technology TERA-BIT STORAGE 2.5D high bandwidth and high density DRAM with TSV and Si Interposer 1 tera-bit/cm2 achieved 5 years ahead from roadmaps We are Here

65nm 28nm 14nm Power -50% -80% 65nm 28nm 14nm SCALE DOWN BENEFITS Smaller Faster Less power consumption Cheaper (if you fabricate millions) 65nm 28nm 14nm Power -50% -80% 65nm 28nm 14nm

SCALE DOWN BENEFITS Maximum die size One Core One core AMD dual core 65nm Intel Octa core 22nm 8 cores instead of 1 using the same space 3 times faster 10 times less power consumption

High-K, low-K dielectric, Airgap Metal gate FinFET TECHNOLOGY INNOVATION & COST Strain, eSiGe, High-K, low-K dielectric, Airgap Metal gate FinFET Double, quad patterning

TECHNOLOGY TRENDS TOWARDS BILLION $ FAB

10-NM CHIPS Samsung Exynos 8895 in 10-nm IBM, GlobalFoundries, Samsung, SUNY first 7-nm testchip Samsung Snapdragon 635 in 10-nm

TECHNOLOGY INNOVATION & COST Less and less companies in the 14-nm market Keynote_Ajit Manocha_GLOBALFOUNDRIES

Embedded SiGe (e-SiGe) Improved p mobility High K gate dielectric TECHNOLOGY INNOVATION & COST Main target Type of innovation First order effect Device performance Strain Improved n mobility Embedded SiGe (e-SiGe) Improved p mobility High K gate dielectric Increased field effect Metal gate Decreased leakage FinFET Higher current density Interconnect performance Low K inter dielectrics Reduced crosstalk and delay Local interconnect Higher density Manufacturability Double patterning Improved yield

ROADMAP ACCORDING TO TSMC Research at TSMC Description Schedule 10nm logic platform technology and applications 3rd generation FinFET CMOS platform technology for System-on-chips (SoC) 2016 7nm logic platform technology and applications 4th generation FinFET CMOS platform technology for System-on-chips 2017 3D IC Cost-effective solution with better form factor and performance for System-in-package (SiP) 2016 ~ 2017 Next-generation lithography EUV and multiple e-beam to extend Moore’s Law 2016 ~ 2019 Long-term research SoC technology and transistors for 5nm node and beyond 2015 ~ 2019 http://www.tsmc.com/english/dedicatedFoundry/technology/future_rd.htm

Upper MEM MEM to SoC (TMV) PCB PCB MEM to PCB (TMV) Bottom SoC GOING 3D – Package on Package Upper MEM SoC to PCB MEM to SoC (TMV) MEM to PCB (TMV) PCB PCB Bottom SoC E. Sicard, EMC performance analysis of a Processor/Memory System using PCB and Package-On-Package, EMC Compo 2015 Edinburgh

Processor die GOING 3D – Stacked Dies THERE IS PLENTY OF SPACE ON THE TOP 3D technology uses stacked dies, through-silicon-vias Enables 10-20 Gb/s/pin at 1.0V Samsung 3D (Galaxy 6) vs PoP (Galaxy 5) : 30% faster 20% less power Less heat Thinned memory die 10 µm Multicore 350 µm thickness Direct bond interconnect (DBI) Package leadframe (GND) Through Silicon Via (TSV) Possible 3rd die Bottom die Upper die http://www.youtube.com/watch?v=Rw9fpsigCfk