CMOS Devices PN junctions and diodes NMOS and PMOS transistors

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Presentation transcript:

CMOS Devices PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Bipolar transistors

PN Junctions Diffusion causes depletion region D.R. is insulator and establishes barrier This leads to 1-directional current flow Forms junction capacitor Capacitance highly voltage dependent Can be nuisance or benefits

PN Junctions

PN Junctions Initial impurity concentration

PN Junctions

PN Junctions Depletion region widths: Barrier potential:

Note the large magnitude of the field Example NA=10^15 atoms/cm^3, ND=10^16, vD=-10 Ni=2.25*10^20 Phi_o=26ln(10^15*10^16/2.25/10^20)=638mV xp= - 3.5 mm xn= 0.35 mm Max field = q*NA*xp/e = -5.4*10^4 V/cm Note the large magnitude of the field

PN Junctions The depletion charge The junction capacitance

Can be used as voltage controlled capacitor Here m = 1/2 for the step change in impurity concentration. For gradual concentration change, m = 1/3.

Impurity concentration profile for diffused pn junction

Current density at boundary due to wholes: Total: Diode current:

The MOS Transistor

TWO TYPES OF TRANSISTORS

CMOS Transistors

Capacitors Two conductor plates separated by insulator for a capacitor Intentional capacitors vs parasitic capacitors Linear vs nonlinear capacitors Linear capacitors:

Integrated Capacitors in CMOS High density, good matching, but nonlinear

High density, good matching, good linearity, but require two-poly processes

Other Caps Cgs of enhancement transistors metal to poly metal to metal PN junction diffusion to substrate side wall Fringe caps from top layer metals

Layering strategies

Parasitic Capacitors

Proper layout of capacitors For achieving CA = 2CB, which one is better?

Various Capacitor Errors

Resistors in CMOS Diffusion resistor polysilicon resistor well resistor metal layer resistor contact resistor

Diffusion resistor in n-well

Polysilicon resistor on FOX

n-well resistor on p-substrate

Bipolar in CMOS PNP

CMOS Transistors

Latch-up problem

Preventing Latch-up

Preventing Latch-up

ESD protection A very serious problem Not enough theoretical study Many trade secrets Learn from experienced designers

reset CLK S1 S16 S2 S15 S3 S14 S4 S13 S5 S12 S6 S11 S7 S10 S8 S9 S R C D Q reset CLK S1 S16 S2 S15 S3 S14 S4 S13 S5 S12 S6 S11 S7 S10 S8 S9