ECE 3430 – Intro to Microcomputer Systems ECE 3430 – Introduction to Microcomputer Systems University of Colorado at Colorado Springs Lecture #19 Agenda Today: Electrical Test and Measurement Equipment Additional HC11 Features (SPI and SCI) Lecture #19 ECE 3430 – Intro to Microcomputer Systems Fall 2009

Test and Measurement Equipment Test Equipment in General: - In all designs, there must be a way to test the circuitry.  Prototype Turn-On / Debug  Verification - In this class, we deal with debug at the system level (i.e., multiple components talking to each other): Component Component Wire or PCB (printed circuit board) RAM HC11 A/D Wires LCD Lecture #19 ECE 3430 – Intro to Microcomputer Systems Fall 2009

Test and Measurement Equipment Oscilloscopes: - This is a device that will show the analog representation of what’s going on. - Today’s oscilloscopes are digitizing. This means they use an A/D converter to acquire the waveform and then redraw it on their screen using bits stored in memory. - The waveform information is stored and processed internally by the oscilloscope in digital format. - This allows uP/uC devices to do the waveform analysis—rather than depending on custom analog electronics. Component Component Probe Point Lecture #19 ECE 3430 – Intro to Microcomputer Systems Fall 2009

Test and Measurement Equipment Oscilloscopes: - Architecture: - Time base: A clock that tells the A/D when to sample. - Trigger: Point in the data record that is defined as t=0. Triggers allow the oscilloscope to stabilize the display output. Triggers can be generated internally in the scope or provided externally via a cable. Triggers must be periodic! PC Display RAM Memory Controller A/D RAM RAM Time base Trigger Lecture #19 ECE 3430 – Intro to Microcomputer Systems Fall 2009

Test and Measurement Equipment Oscilloscopes (displaying data): Display screen is divided into a grid. Each vertical division represents a certain amount of voltage. Each horizontal division represents a certain amount of time. A volts/division and time/division control allow the user to “zoom in” on different parts of the waveform. voltage time Lecture #19 ECE 3430 – Intro to Microcomputer Systems Fall 2009

Test and Measurement Equipment Oscilloscope Specs: Bandwidth – The analog bandwidth of the scope. This is the fastest frequency that can get into the scope (be seen by the scope). Sample Rate – Rate at which the data is sampled. The Nyquist sampling theorem states that in order to faithfully reconstruct a signal from a series of samples, the rate at which the samples were taken must be at least twice the frequency of the highest frequency component of the original signal. All electrical signals can be decomposed into a series of sinusoids (or frequency components). In modern oscilloscopes, manufacturers usually give us at least a 4x sampling rate. The sampling rate can be changed so that if you are looking at slower frequency signals, you can achieve a longer acquisition record. Lecture #19 ECE 3430 – Intro to Microcomputer Systems Fall 2009

Test and Measurement Equipment Oscilloscopes: Making a scope measurement? 1) Check that scope has enough bandwidth to measure your signal. 2) Check that the scope has a high enough sample rate and that it is set to what you need. Probes: Probes are the special connectors that attach the oscilloscope to the device under test/measurement. Probes can alter the voltage that is measured—so the oscilloscope must know what kind of probe you’re using so it can compensate for the voltage differences. Probes themselves also have a bandwidth restriction. If you are measuring signals with high frequency components, you must have a good grade probe (passive vs. active probes). Lecture #19 ECE 3430 – Intro to Microcomputer Systems Fall 2009

Test and Measurement Equipment Logic Analyzers: - This is a device that will show the digital representation of what’s going on. Component Component Probe Point Display only shows visual representation of bits (0 and 1)! Analog voltage is “rounded” to 0 or 1! Lecture #19 ECE 3430 – Intro to Microcomputer Systems Fall 2009

Test and Measurement Equipment Logic Analyzers: - Architecture: - Some useful features of a logic analyzer: 1) Search for patterns (even very complex patterns). 2) Filter out data that you don’t want to store in memory. This way you have more meaningful info displayed. 3) Analyze bus transactions (see what a CPU is executing). Display PC RAM Acquisition IC Memory Controller Comparator RAM RAM (Converts input data to ‘1’ or ‘0’ using “programmable” reference voltage) (latches and looks for pattern) Lecture #19 ECE 3430 – Intro to Microcomputer Systems Fall 2009

Test and Measurement Equipment Logic Analyzers (triggering): A trigger in an oscilloscope is a periodic event (such as a voltage of a periodic waveform rising above a certain threshold). A trigger in a logic analyzer is a generic event telling the analyzer to start capturing data across all the data channels. In modern logic analyzers, triggers can be complex situations such as: Wait until signal number 1 goes high, then wait until signals 2-3 have gone low, and finally wait until signal 4 has gone high for at least 500 ns. Use your imagination—virtually any combination of events is possible (at least with high grade logic analyzers). Lecture #19 ECE 3430 – Intro to Microcomputer Systems Fall 2009

Test and Measurement Equipment Logic Analyzers (modes of operation): Logic analyzers generally operate in one of two modes: State mode Timing mode In state mode, an external clock is provided to the logic analyzer via a dedicated input. When this clock is pulsed, the logic analyzer samples all data on the other inputs. This is useful when trying to capture synchronous data (transactions on a bus for example). In timing mode, the logic analyzer continually gathers data on all input pins as quickly as it can until it runs out of acquisition memory. Generally driven by an internal clock. Lecture #19 ECE 3430 – Intro to Microcomputer Systems Fall 2009

Test and Measurement Equipment Logic Analyzer Specs: Maximum Toggle Frequency – This tells how fast of a digital signal the logic analyzer can acquire (usually different for state and timing modes). # of Channels – Since we are only storing 1’s and 0’s, we can acquire many more signals. Today’s analyzers can simultaneously monitor hundreds of signals in the same clock domain. Memory Depth – This tells how many bits of memory per channel the analyzer can store. Today’s analyzers can capture millions of bits per channel. Lecture #19 ECE 3430 – Intro to Microcomputer Systems Fall 2009

Additional HC11 Features HC11 Modes of Operation: Single Chip Mode - The HC11 functions without external address and data buses. All SW needed is contained in internal memories. Internal program and data memory is used. A true “microcomputer on a chip” solution. Expanded Mode - The HC11 has the ability to access a 64KB address space (16 address lines). We are currently using this mode in the lab. The 8K external EEPROM (which we use for program storage) is mapped into the 64KB address space at $E000. Bootstrap Mode - The HC11 has 192 byte bootstrap ROM where a “bootloader” program is located. It appears as internal memory ($BF40 - $BFFF). This program uses the serial communication interface (SCI) to read a new program into the on-chip RAM. Useful for programming EEPROMs on-the-fly. Special Test Mode – Only used during Motorola’s/Freescale’s production testing. Lecture #19 ECE 3430 – Intro to Microcomputer Systems Fall 2009

Additional HC11 Features Serial Communication Interface (SCI): - The HC11 has internal circuitry that can communicate using the EIA-232/RS-232 protocol. This circuitry can communicate directly with a EIA-232 interface circuit. This interface circuit can communicate directly with a printer, modem, or terminal program (HyperTerminal or comterm.exe). The EIA-232 interface circuit (and transceiver) is located on the MicroStamp docking module. - This protocol uses 2 lines that are shared with Port D pins PD0 = RxD = Receive Data PD1 = TxD = Transmit Data - There are internal control registers in the HC11 used to configure and communicate with the SCI: SCI Control Register 1 (SCCR1), SCI Control Register 2 (SCCR2) SCI Data Register (SCDR), SCI Status Register (SCSR) Lecture #19 ECE 3430 – Intro to Microcomputer Systems Fall 2009

Additional HC11 Features Serial Peripheral Interface (SPI): - The HC11 has circuitry that can be used to communicate between multiple HC11’s and any other device that has the SPI interface circuitry. - This protocol uses 4 pins that are shared with Port D: PD2 = MISO (master in / slave out) PD3 = MOSI (master out / slave in) PD4 = SCK (SPI clock) PD5 = SS (slave select) - There are three internal control registers that are used to configure and communicate with the SPI: Serial Peripheral Interface Control Register (SPCR) Serial Peripheral Interface Data Register (SPDR) Serial Peripheral Interface Status Register (SPSR) Lecture #19 ECE 3430 – Intro to Microcomputer Systems Fall 2009

Additional HC11 Features Serial Peripheral Interface (SPI): SPI-compliant devices are attached in a ring. Only one device is a master device. All others are slave devices. Only the master is allowed to initiate a data transfer. Each SPI data transfer is 8-bits. Multiple SPI data transfers are used to transfer more than 8-bits. Interface method #1 (SS pulled up on master, SS grounded on slaves): Master Slave #1 Slave #2 MOSI MOSI MISO MOSI MISO SCK SCK SCK MISO n connected slaves… Lecture #19 ECE 3430 – Intro to Microcomputer Systems Fall 2009

Additional HC11 Features Serial Peripheral Interface (SPI): Interface method #2 (SS pulled up on master): Master Slave #1 MOSI MOSI MISO SCK SS SCK SCK Slave #2 MOSI MISO SS MISO General Purpose Output 1 n connected slaves… General Purpose Output 2 Lecture #19 ECE 3430 – Intro to Microcomputer Systems Fall 2009

Additional HC11 Features Serial Peripheral Interface (SPI): Interface method #1: Each SPI device is connected in one continuous chain. All data transfers initiated by the master. To send data to slave #2, the data must shift through slave #1 first. For slave #1 to send “reply” data to the master, the data must go through slave #2. Very similar to JTAG chain or, conceptually, a big shift register. Interface method #2: Each SPI device is connected directly to the master (not the other slaves). The master can send data directly to any of the slaves by asserting the SS line. The slave can send “reply” data directly back to the master. Why would one be better than the other? Lecture #19 ECE 3430 – Intro to Microcomputer Systems Fall 2009