A 3D deep n-well CMOS MAPS for the ILC vertex detector 1 Università di Pavia Dipartimento di Elettronica, I-27100 Pavia, Italy 3 Università di Bergamo Dipartimento di Ingegneria Industriale, I-24044 Dalmine (BG), Italy 2 INFN Sezione di Pavia I-27100 Pavia, Italy L. Gaioni1,2, M. Manghisoni2,3, L. Ratti1,2, V. Re2,3 G. Traversi2,3 luigi.gaioni@unipv.it, massimo.manghisoni@unibg.it, lodovico.ratti@unipv.it, valerio.re@unibg.it, gianluca.traversi@unibg.it Introduction This work presents the features of a new kind of deep n-well monolithic active pixel sensor (DNW-MAPS), namely SDR1 (Sparsied Data Readout), which exploits the capabilities of vertical integration (3D) processing in view of the design of a high granularity detector for vertexing applications at the International Linear Collider. SDR1 features a 240x256 matrix of two vertically integrated layers, each fabricated in a 130 nm CMOS process, containing the analog and the digital front-end respectively, with a pixel pitch of 20 μm. The analog tier includes a charge sensitive amplifier and a threshold discriminator, while the digital front-end is able to keep information about two hits during each single bunch train with the relevant time stamps (5 bit resolution), thus providing a high detection efficiency. Collection efficiency turns out to be significantly better than in the planar (2D) version of the chip as a consequence of the separation of the analog and digital electronics and the reduction of the area covered by competitive n-wells in the analog tier. The SDR1 chip Analog front-end Analog section Digital section DNW sensor P-well N-well NMOS PMOS DNW sensor N-well Inter-tier connections Analog section and discriminator NMOS CF Vfbk AGND DVDD AVDD DGND Vt TIER 1 (BOTTOM) TIER 2 (TOP) shaperless FE (SFE) discriminator Inter-tier bond pads CD 3D DNW MAPS matrix, 240x256, 20 μm pitch pixels Processes provided by Chartered/Tezzaron Semiconductor Two vertically integrated layers each fabricated in a 130 nm CMOS process, including analog and digital section Tier 1 includes collecting electrode (deep n-well/p-substrate junction), analog front end and NMOS from discriminator Tier 2 includes digital front end (2 latches for hit storage, sparsification logic, 2 time stamp registers, kill mask), digital back-end (X and Y registers, time stamp line drivers, serializer) and PMOS from discriminator Separation of analog from digital section minimizes crosstalk between digital blocks and sensor/analog circuits Reduced area covered by competitive n-wells in the analog tier W/L input device: 20/0.18 Power consumption: 5 μW Equivalent noise charge: 35 e- @ CD = 200 fF Threshold dispersion: 36 e- (main contributions from preamplifier input device and NMOS and PMOS pair in the discriminator) Charge sensitivity: 800 mV/fC Power Down option for power saving Preamplifier response to an 800 e- pulse Monte Carlo simulations Digital front-end and sparsified readout architecture gX TS tko gY tki Y=1 Y=2 Y=240 X=256 X=2 X=1 MUX FirstTokenIn LastTokenOut DataOut TSBUF ReadOutCLK Time stamp counter gX=GetX gY=GetY TS=TimeStampOut tki=TokenIn tko=TokenOut 8 5 D NQ Q R S K CP FFSRK FFDR FFD KillMaskClk KillMaskIn KillMaskOut ST RO_EN T_IN T_O time stamp register NRO_EN TokenOut 5 GetX GetY TimeStampOut CellClk NMasterReset NLatch Enable Token In Time Stamp HIT NHIT Monte Carlo simulations on clusters of 3x3 DNW MAPS featuring the layout of a 2D cell and SDR1 sensors (10000 experiments, 80 μm thick substrate) NW 2D DNW-MAPS cell SDR1 cell (bottom tier) 25 mm 20 mm DNW (collecting electrode) Two different processing phases: detection phase (corresponding to the bunch train period) readout phase (corresponding to the intertrain period) During the detection phase the time stamp is sent to all cells The SR FF (FFSRK) is set when the pixel is hit the first time and the relevant time stamp register gets frozen Upon a second hit, the D FF (FFDR) is set and the relevant time stamp register gets frozen At the end of the detection phase a token is launched and sparse readout is performed During the readout phase, the hit cell, after the arrival of the token, sends both the coordinate and time stamp data to the output serializer at the next cell clock rising edge; data are serialized and transmitted off the chip within a cell clock period (1 CellClk/hit) Placing most of the PMOS on the digit layer may reduce the area covered by competitive electrodes  better efficiency The DNW covers about 35% of the cell area in the 2D chip, more than 50% in SDR1 Digital section and discriminator PMOS Inter-tier connections 11th Pisa Meeting on Advanced Detectors, May 24-30 2009, La Biodola, Isola d'Elba (Italy)