A 3D deep n-well CMOS MAPS for the ILC vertex detector

Slides:



Advertisements
Similar presentations
Latest Developments from the CCD Front End LCWS 2005 Stanford Joel Goldstein, RAL for the LCFI Collaboration.
Advertisements

Incontri di Fisica delle Alte Energie, IFAE 2006, Pavia, 19 – 21 aprile Sensori a pixel attivi monolitici in tecnologia CMOS 130 nm V. Re b,c, C.
1 1 Università degli Studi di Pisa, 2 INFN Pisa, 3 Scuola Normale Superiore di Pisa, 4 Università degli Studi di Pavia, 5 INFN Pavia, 6 Università degli.
Snowmass 2005 SOI detector R&D Massimo Caccia, Antonio Bulgheroni Univ. dell’Insubria / INFN Milano (Italy) M. Jastrzab, M. Koziel, W. Kucewicz, H. Niemiec.
NA62 front end Layout in DM option Jan Kaplon/Pierre Jarron.
3D Vertex Detector Status The requirement for complex functionality in a small pixel led us to investigate vertically integrated (3D) processes. Developed.
Università degli Studi di Pavia and INFN Pavia
1 Digital Active Pixel Array (DAPA) for Vertex and Tracking Silicon Systems PROJECT G.Bashindzhagyan 1, N.Korotkova 1, R.Roeder 2, Chr.Schmidt 3, N.Sinev.
Development of an ASIC for reading out CCDS at the vertex detector of the International Linear Collider Presenter: Peter Murray ASIC Design Group Science.
VIP1: a 3D Integrated Circuit for Pixel Applications in High Energy Physics Jim Hoff*, Grzegorz Deptuch, Tom Zimmerman, Ray Yarema - Fermilab *
Beam Tests of 3D Vertically Interconnected Prototypes Matthew Jones (Purdue University) Grzegorz Deptuch, Scott Holm, Ryan Rivera, Lorenzo Uplegger (FNAL)
C. Andreoli, A. Bulgheroni, C. Cappellini, M. Caccia, L. Gaioni, M. Jastrzab, M. Manghisoni, E. Pozzati, L. Ratti, V. Re, F. Risigo, V. Speziali, G. Traversi.
L. Ratti a,c, E. Pozzati a,c, C. Andreoli a,c, M. Manghisoni b,c, V. Re b,c, V. Speziali a,c, G. Traversi b,c a Università degli Studi di Pavia b Università.
Valerio Re - LCWS 2008, UIC, November 16-20, Status and perspectives of Deep N-Well CMOS MAPS for the ILC Vertex Detector Valerio Re Università.
Valerio Re, Massimo Manghisoni Università di Bergamo and INFN, Pavia, Italy Jim Hoff, Abderrezak Mekkaoui, Raymond Yarema Fermi National Accelerator Laboratory.
65 nm CMOS analog front-end for pixel detectors at the HL-LHC
The development of the readout ASIC for the pair-monitor with SOI technology ~irradiation test~ Yutaro Sato Tohoku Univ. 29 th Mar  Introduction.
CMOS MAPS with pixel level sparsification and time stamping capabilities for applications at the ILC Gianluca Traversi 1,2
Fermilab Silicon Strip Readout Chip for BTEV
Pixel detector development: sensor
G. Traversi, M. Manghisoni, L. Ratti, V. Re, V. Speziali Vertex 2007 – 16 th International Workshop on Vertex Detectors September 23 – 28, 2007 – Lake.
Eleuterio SpiritiILC Vertex Workshop, April On pixel sparsification architecture in 130nm STM technology ILC Vertex Workshop April 2008 Villa.
Ideas for a new INFN experiment on instrumentation for photon science and hadrontherapy applications – BG/PV group L. Ratti Università degli Studi di Pavia.
L. Ratti a,b, M. Dellagiovanna a, L. Gaioni a,b, M. Manghisoni b,c, V. Re b,c, G. Traversi b,c, S. Bettarini d,e, F. Morsani e, G. Rizzo d,e a Università.
S.Zucca a,c, L. Gaioni b,c, A. Manazza a,c, M. Manghisoni b,c, L. Ratti a,c V. Re b,c, E. Quartieri a,c, G. Traversi b,c a Università degli Studi di Pavia.
Analog front-end for vertically integrated hybrid and monolithic pixels L. Ratti Università degli Studi di Pavia and INFN Pavia XV SuperB General Meeting.
V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, Forecasting noise and radiation hardness of CMOS front-end electronics.
Analysis of 3D Stacked Fully Functional CMOS Active Pixel Sensor Detectors (1) Istituto Nazionale di Fisica Nucleare Sezione di Perugia – Italy Sezione.
Laboratorio di Strumentazione Elettronica Annual Report of Activities – a.a. 2009/2010 – October 15, 2010Phone Meeting – October 29, 2010 Characterization.
The SuperB Silicon Vertex Tracker Abstract : The SuperB project aims to build an asymmetric e+ - e- collider capable of reaching.
The design of fast analog channels for the readout of strip detectors in the inner layers of the SuperB SVT 1 INFN Sezione di Pavia I Pavia, Italy.
End OF Column Circuits – Design Review
M. Manghisoni, L. Ratti Università degli Studi di Pavia INFN Pavia
Valerio Re Università di Bergamo and INFN, Pavia, Italy
3D CMOS monolithic 3-bit resolution pixel sensor with fast digital pipelined readout Olav Torheim, Yunan Fu, Christine Hu-Guo, Yann Hu, Marc Winter.
Ivan Peric, Christian Kreidl, Peter Fischer University of Heidelberg
10-12 April 2013, INFN-LNF, Frascati, Italy
Silicon eyes for radio-labeled biological samples
Pixel front-end development
Activities in Pavia/Bergamo on Layer0 pixels
Charge sensitive amplifier
M. Manghisoni, L. Ratti, V. Re, V. Speziali, G. Traversi
L. Rattia for the VIPIX collaboration
Giuliana Rizzo INFN and University, Pisa on behalf of SVT-SuperB group
INFN Pavia and University of Bergamo
V. Reb,c, C. Andreolia,c, M. Manghisonib,c, E. Pozzatia,c, L
Radiation Tolerance of a 0.18 mm CMOS Process
INFN Pavia / University of Bergamo
Deep N-well 130nm CMOS MAPS for the ILC vertex detector Valerio Re
A 12 µm pixel pitch 3D MAPS with delayed and full serial readout for the innermost layer of ILC vertex detector Yunan Fu (on behalf of the CMOS Sensor.
L. Ratti, M. Manghisoni Università degli Studi di Pavia INFN Pavia
Status of the Chronopixel Project
HV-MAPS Designs and Results I
L. Ratti V SuperB Collaboration Meeting
Activities on MAPS at INFN Roma Tre
The SuperB Silicon Vertex Tracker
Activities in Pavia/Bergamo on SVT strip readout and on Layer0 pixels
Mimoroma2 MAPS chip: all NMOS on pixel sparsification architecture
Update on microstrip front-end and Layer0 pixel upgrade
Status & perspectives of the R&D on DNW MAPS
MAPS with advanced on-pixel processing
SVT detector electronics
Monolithic active pixel sensors in a 130 nm triple well CMOS process
Analog Front-end electronics for the outer layers of the SuperB SVT: design and expected performances Luca Bombelli1,2 on behalf of the SVT-SuperB Group.
OmegaPix 3D IC prototype for the ATLAS upgrade SLHC pixel project 3D Meeting 19th March, 2010 A. Lounis, C. de La Taille, N. Seguin-Moreau, G.
Signal processing for High Granularity Calorimeter
Readout Electronics for Pixel Sensors
Stefano Zucca, Lodovico Ratti
Readout Electronics for Pixel Sensors
Readout Electronics for Pixel Sensors
Presentation transcript:

A 3D deep n-well CMOS MAPS for the ILC vertex detector 1 Università di Pavia Dipartimento di Elettronica, I-27100 Pavia, Italy 3 Università di Bergamo Dipartimento di Ingegneria Industriale, I-24044 Dalmine (BG), Italy 2 INFN Sezione di Pavia I-27100 Pavia, Italy L. Gaioni1,2, M. Manghisoni2,3, L. Ratti1,2, V. Re2,3 G. Traversi2,3 luigi.gaioni@unipv.it, massimo.manghisoni@unibg.it, lodovico.ratti@unipv.it, valerio.re@unibg.it, gianluca.traversi@unibg.it Introduction This work presents the features of a new kind of deep n-well monolithic active pixel sensor (DNW-MAPS), namely SDR1 (Sparsied Data Readout), which exploits the capabilities of vertical integration (3D) processing in view of the design of a high granularity detector for vertexing applications at the International Linear Collider. SDR1 features a 240x256 matrix of two vertically integrated layers, each fabricated in a 130 nm CMOS process, containing the analog and the digital front-end respectively, with a pixel pitch of 20 μm. The analog tier includes a charge sensitive amplifier and a threshold discriminator, while the digital front-end is able to keep information about two hits during each single bunch train with the relevant time stamps (5 bit resolution), thus providing a high detection efficiency. Collection efficiency turns out to be significantly better than in the planar (2D) version of the chip as a consequence of the separation of the analog and digital electronics and the reduction of the area covered by competitive n-wells in the analog tier. The SDR1 chip Analog front-end Analog section Digital section DNW sensor P-well N-well NMOS PMOS DNW sensor N-well Inter-tier connections Analog section and discriminator NMOS CF Vfbk AGND DVDD AVDD DGND Vt TIER 1 (BOTTOM) TIER 2 (TOP) shaperless FE (SFE) discriminator Inter-tier bond pads CD 3D DNW MAPS matrix, 240x256, 20 μm pitch pixels Processes provided by Chartered/Tezzaron Semiconductor Two vertically integrated layers each fabricated in a 130 nm CMOS process, including analog and digital section Tier 1 includes collecting electrode (deep n-well/p-substrate junction), analog front end and NMOS from discriminator Tier 2 includes digital front end (2 latches for hit storage, sparsification logic, 2 time stamp registers, kill mask), digital back-end (X and Y registers, time stamp line drivers, serializer) and PMOS from discriminator Separation of analog from digital section minimizes crosstalk between digital blocks and sensor/analog circuits Reduced area covered by competitive n-wells in the analog tier W/L input device: 20/0.18 Power consumption: 5 μW Equivalent noise charge: 35 e- @ CD = 200 fF Threshold dispersion: 36 e- (main contributions from preamplifier input device and NMOS and PMOS pair in the discriminator) Charge sensitivity: 800 mV/fC Power Down option for power saving Preamplifier response to an 800 e- pulse Monte Carlo simulations Digital front-end and sparsified readout architecture gX TS tko gY tki Y=1 Y=2 Y=240 X=256 X=2 X=1 MUX FirstTokenIn LastTokenOut DataOut TSBUF ReadOutCLK Time stamp counter gX=GetX gY=GetY TS=TimeStampOut tki=TokenIn tko=TokenOut 8 5 D NQ Q R S K CP FFSRK FFDR FFD KillMaskClk KillMaskIn KillMaskOut ST RO_EN T_IN T_O time stamp register NRO_EN TokenOut 5 GetX GetY TimeStampOut CellClk NMasterReset NLatch Enable Token In Time Stamp HIT NHIT Monte Carlo simulations on clusters of 3x3 DNW MAPS featuring the layout of a 2D cell and SDR1 sensors (10000 experiments, 80 μm thick substrate) NW 2D DNW-MAPS cell SDR1 cell (bottom tier) 25 mm 20 mm DNW (collecting electrode) Two different processing phases: detection phase (corresponding to the bunch train period) readout phase (corresponding to the intertrain period) During the detection phase the time stamp is sent to all cells The SR FF (FFSRK) is set when the pixel is hit the first time and the relevant time stamp register gets frozen Upon a second hit, the D FF (FFDR) is set and the relevant time stamp register gets frozen At the end of the detection phase a token is launched and sparse readout is performed During the readout phase, the hit cell, after the arrival of the token, sends both the coordinate and time stamp data to the output serializer at the next cell clock rising edge; data are serialized and transmitted off the chip within a cell clock period (1 CellClk/hit) Placing most of the PMOS on the digit layer may reduce the area covered by competitive electrodes  better efficiency The DNW covers about 35% of the cell area in the 2D chip, more than 50% in SDR1 Digital section and discriminator PMOS Inter-tier connections 11th Pisa Meeting on Advanced Detectors, May 24-30 2009, La Biodola, Isola d'Elba (Italy)