Created by Luis Chioye, Art Kay Presented by Peggy Liska Final Simulations to Test AC Settling TIPL 4405 TI Precision Labs – ADCs Hello, and welcome to the TI Precision Lab covering component selection for SAR ADCs. In the last video we found the final RC charge bucket values for our example design. In this video we will perform several SPICE simulation tests to confirm that the design meets our performance criteria. Created by Luis Chioye, Art Kay Presented by Peggy Liska

Agenda SAR Operation Overview Select the data converter Use the Calculator to find amplifier and RC filter Find the Op Amp Verify the Op Amp Model Building the SAR Model Refine the Rfilt and Cfilt values Final simulations Measured Results SAR Drive Calculator Algorithm This video shows the results of the final simulations generated after following the process for selecting the external components for a SAR ADC.

Expand the acquisition time to check settling Once you have completed the selection of the amplifier and RC circuit you may still need to perform additional simulations to make sure that your design is robust and meets all your design criteria. One common test is to temporarily increase the acquisition time to confirm that the error is really settled. The point here is that it is possible for the error settling waveform to coincidentally pass through zero at the end of the acquisition period. The simulation results on the left show this case. The settling for this example appears to be good as the final error is inside the error target. However, if you take the same circuit and expand the acquisition window, you will see that the signal isn’t really settled. You can see this in the figure on the right. Ideally you want the error signal to be fully settled and do not want to rely upon the error signal crossing through zero at the end of the acquisition period. The problem is that process variation may cause the response to change and the error may not cross through zero at the end of acquisition. It should be noted that a small settling error after the end of acquisition is acceptable as long as it doesn’t exceed one half of an LSB. Finally, don’t forget to set the acquisition time back to the specified value at the end of this test. This adjustment is for the simulation of settling time only and does not apply to the real circuit. Don’t count on luck! The signal isn’t really settled. The error is less than ½ LSB (-30uV). Will this circuit work? tacq change in simulation only to test for marginal design. Not adjusted in real circuit.

Look at Op Amp Settling Another approach to looking at settling beyond the end of the acquisition period is to look at the op amp output. This serves a similar purpose to expanding the acquisition period in that a robust design’s op amp output will be settled to one half LSB at the end of the acquisition period. Amplifier settled to ½ LSB or better after tacq ends.

Check settling for multiple cycles Make sure that settling is consistent from cycle to cycle. Always discard the first cycle. Another verification is to make sure that the settling doesn’t change across multiple cycles. You should always discard the first cycle as this contains start-up errors. Some designs will have a long term settling error that creates inconsistent results from sample to sample. Ideally you want all conversion results to be consistent after the first cycle.

AC Input Signal Simulation Example Up to this point our simulations have all included a dc input signal. This makes it easy to optimize the RC charge bucket circuit, but may not match your real world conditions. Generally, circuits designed using the method we covered will also work well in ac simulation, but it is best to confirm. To do this you will have to change the input signal from a DC source to an AC source. Also, we will want to compare the sampled signal across the sample and hold capacitor to an AC signal. However, to do an accurate comparison, we will have to take into account the phase shift of all the RC circuitry as well as the offset and phase shift of the amplifier. PROBLEM: The phase shift introduced by the amplifier and the RC circuitry make it difficult to estimate the error or settling signal

Results for an AC Simulation: What about error This graph shows the results for an AC simulation for the previous circuit. You can see many acquisition periods and the sample and hold circuit tracks the input signal for each acquisition period. You can also see charge kickback spikes on the filter output voltage. The one thing that we don’t show here is the error signal. In the next slide we will zoom in on these signals and see how a phase shift can impact error.

AC Input Signal Simulation Example Vfilt Vin This slide zooms in on the AC simulation results. You can see that the sample and hold signal tracks the filter signal well during acquisition and holds at the end of acquisition . Notice how the input signal does not track the filter signal. There is a phase shift from the filter and also from the internal sampling network. Because of the phase shift, we cannot simply compare the input signal to the sample and hold voltage to calculate an error. Vsh PROBLEM: The phase shift introduced by the amplifier and the RC circuits make it difficult to estimate the settling error in the sample and hold

AC Input Simulation Example S/H switching with conversions This circuit shows how to check error in an AC SAR simulation. The top path for this circuit is the standard amplifier and sample and hold circuit that we developed earlier. The bottom circuit is the same as the top circuit except that the acquisition switch is permanently shorted and there is no end of conversion reset switch. In other words, the bottom circuit has all the phase delay’s from the top circuit but none of the switched sample and hold behavior. The bottom is an “ideal” signal that we can compare the sampled signal with. Noticed the voltage controlled voltage source is used to compare the sampled and ideal signal to generate the error signal. “Ideal” signal Sees phase shift without sample and hold

AC Input Signal Simulation Example “Ideal” Signal from non-switching S/H Phase difference no longer present “Ideal” Signal from non-switching S/H This slide shows the sample and hold signal compared to the ideal signal that includes the phase shift. Notice that now the ideal signal tracks the input well whereas before there was a significant error from the phase delay of the RC filter. Sampled Signal Solution: The “Ideal” Signal generated from non-switching S/H has same phase as the Sampled Signal; allowing the calculation of settling errors Sampled Signal

Check the error for AC simulations Place the cursor at the end of an acquisition cycle. Generate a legend. The error should be less than ½ LSB. Check the error at multiple locations To properly test the AC error you should look at error at several points on the sine wave. Make sure you check where the sine wave moves fastest, e.g. 45⁰, 135⁰, 225⁰, 315⁰. As we did previously, the error needs to be examined immediately at the end of the acquisition period. In this example, you can see the cursor is set to the end of the acquisition period and a legend is created. The legend lists the value of all the signals at this point in time. In this case, you can see that the error signal is 14uV which is well within the one half LSB error target.

Agenda – next video… SAR Operation Overview Select the data converter Use the Calculator to find amplifier and RC filter Find the Op Amp Verify the Op Amp Model Building the SAR Model Refine the Rfilt and Cfilt values Final simulations Measured Results SAR Drive Calculator Algorithm The next video will walk through the measured results for the circuit from this simulation.

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