PADME L0 Trigger Processor M. Raggi Sapienza Universita’ di Roma TDAQ WG PAMDE collaboration meeting LNF 17/1/2017

PADME L0 trigger scheme The trigger rate at PADME will be very low just 50Hz The trigger is provided by the LINAC at each bunch The DAQ system is able to cope with the entire data rate produced PADME trigger sources are: “Physics” all of the bunch delivered will be acquired Cosmic ray trigger (to perform Ecal calibrations) Software and Random trigger (to monitor the Digitizers pedestal) The L0TP should provide the logical OR of the input signal as output L0 trigger processor output Need to provide 2 NIM/TTL synchronized signal for each Digitizer (~64) Need to keep synchronization and output to output signal jitter below 150-200 ps Mauro Raggi - Sapienza Università di Roma

PADME TDAQ scheme PADME on-line computing model 3 L1 DAQ Event build Target 32ch FADC Spectrometer Veto 192 ch FADC High Energy Positron Veto 32ch FADC ECAL 616 ch FADC SAC 49 ch FADC TPix 65536 ch TBD L1 DAQ 1 process per DAQ board L0 DAQ 1 process per DAQ board ADC zero suppression (?) L0 Trigger Processor BTF Beam 50Hz Cosmics 10-20Hz SW/Random L1 DAQ Event build Temporary disk buffer Neutral Filter (Inv) 1 or more ECAL clusters Charged Filter (Vis) 2 or more tracks RAW data Trigger signal Data flow Central Data Recording Facility CNAF (+LNF?) PADME experiment site PADME on-line computing model 3 3 Mauro Raggi - Sapienza Università di Roma

Read out board CAEN V1742 CAEN V1742 Sampling frequency 5Gs/s 12bits for 1V dynamic 1024 samples (200ns) Includes 4 DSR4 digitizing chips Mauro Raggi - Sapienza Università di Roma

Connections L0 to V1742 Fast Trigger connection The trigger inputs of the fast trigger are digitized together with the rest of the signals and allow to get precise timing of the trigger signals. These signals need to be provided by the L0TP Clock synchronization input PADME clock source is distributed to all boards in daisy chain using these input output connections Could the clock be provided by L0TP? Mauro Raggi - Sapienza Università di Roma

Trigger source Physics The L0 Trigger source “Physics” is provided from the LINAC signals at each bunch arrival. The trigger timing with respect to real beam arrival can be adjusted with a digital delay The distribution in time of real signals in the boards depends on the programmed bunch length from 3-200ns. Trig Acquisition window Signals Depending on the detector the acquisition window may vary from 400-1000 ns How to se a unique delay? Mauro Raggi - Sapienza Università di Roma

Trigger source cosmics To monitor the stability of the calorimeter response a cosmic ray telescope will be placed around the ECAL Trigger from a cosmic station is the OR of all the single fingers The coincidence of two station creates a signal to L0TP Can the logic be implemented in the L0TP itself? Cosmic 1 Cosmic Cx=OR 16 In C1 C1&C2 ECal Cosmic trigger C2 Cosmic 2 Mauro Raggi - Sapienza Università di Roma

SW or Random trigger Software trigger: Random trigger: V1742 pedestal are instable and need to be monitored To collect pure pedestal events we plan to produce triggers in the inter-bunch period to collect a sample of pedestal events This trigger need to be inhibited when any other trigger is active to avoid collecting signal events Can be correlated with a Physics events (just delayed) Random trigger: Can be used to collect auto-pass events Mauro Raggi - Sapienza Università di Roma

L0TP scheme 62 trigger signals needed to read out all the PADME detectors Target 1 FADC 2 L0 Trg Spectrometer Veto 6 FADC 12 L0 Trg High Energy Positron 1 FADC 2 L0 Trg ECAL 20 FADC 40 Trg 0 SAC 2 FADC 4 L0 Trg TPix 65536 ch TBD Central Clock L0 Trigger Processor BTF Beam 50Hz Cosmics 10-20Hz SW/Random 64 Trig out Clock out L0 Trigger Processor BTF Beam 50Hz NIM/TTL Cosmics 10-20Hz NIM/TTL/LVDS SW/Random Central Clock Mauro Raggi - Sapienza Università di Roma

L0TP scheme integrated 62 trigger signals needed to read out all the PADME detectors Target 1 FADC 2 L0 Trg Spectrometer Veto 6 FADC 12 L0 Trg High Energy Positron 1 FADC 2 L0 Trg ECAL 20 FADC 40 Trg 0 SAC 2 FADC 4 L0 Trg TPix 65536 ch TBD L0 Trigger Processor BTF Beam 50Hz Cosmics 10-20Hz Clock out 64 Trig out L0 Trigger Processor Central Clock BTF Beam 50Hz NIM/TTL SW/Random Cosmic logic NIM or LVDS from discriminators Mauro Raggi - Sapienza Università di Roma

Clock distribution scheme In the present scheme the readout system is logically divided into left and right sides Each crate contains all the V1742 of Ecal+veto of the Left or Right side The time pix based Beam Monitor has a dedicated electronics The clock is transmitted by the master to each crate The clock is distributed in daisy chains to all boards delay are compensated inside the boards Crate Boards SIDE LF Master clock Clock Crate SIDE R Monitor Mauro Raggi - Sapienza Università di Roma

Possible implementation? Can an FPGA evaluation board + custom analog mezzanine be used? Logic part + Clock distribution source in the FPGA and analog splitting to produce the 64 synchronous trigger signals in a mezzanine? Is a complete custom board the only solution? Mauro Raggi - Sapienza Università di Roma

Conclusions Preliminary requirement for the PADME L0TP are defined Deeper understanding of V1742 board necessary Needs dedicated man power to start implementation studies and project soon. Is an evaluation board+analog Mezzanine suited for the PADME L0TP? Mauro Raggi - Sapienza Università di Roma