16.317 Microprocessor Systems Design I Instructor: Dr. Michael Geiger Fall 2014 Lecture 11: Exam 1 Preview

Microprocessors I: Lecture 11 Lecture outline Announcements/reminders Exam 1: Wednesday, 10/1 Will be allowed calculator, 8.5” x 11” double-sided note sheet x86 instructions covered through last Wednesday are posted HW 3 to be posted Final exam scheduled: Monday, 12/15, 3-6 PM Today’s lecture: Exam 1 Preview General exam notes Review of material 7/19/2018 Microprocessors I: Lecture 11

Microprocessors I: Lecture 11 Exam 1 notes Allowed One 8.5” x 11” double-sided sheet of notes Calculator x86 instruction set (so far) provided for you No other notes or electronic devices (phone, laptop, etc.) Exam will be 50 minutes Will start at 8:00 AM—please be on time! Covers all lectures through last Wednesday General format 1 multiple choice question 2-3 short answer questions 1 extra credit problem 7/19/2018 Microprocessors I: Lecture 11

Microprocessors I: Lecture 11 Test policies Prior to passing out exam, I will verify that you only have one note sheet If you have multiple sheets, I will take all notes You will not be allowed to remove anything from your bag after that point in time If you need an additional pencil, eraser, or piece of scrap paper during the exam, ask me Only one person will be allowed to use the bathroom at a time You must leave your cell phone either with me or clearly visible on the table near your seat 7/19/2018 Microprocessors I: Lecture 11

Review: processor basics; ISA Processor components Microprocessor for computation Input/output to communicate with outside world Storage to hold code/data Instruction set architecture Defines how programmer interfaces with hardware Operations generally fall into one of four groups Data transfer: move data across storage locations Arithmetic: add, subtract, etc. Logical: AND, OR, shifts, etc. Program control: jumps/branches/calls 7/19/2018 Microprocessors I: Lecture 11

Microprocessors I: Lecture 11 Review: ISA, storage Instruction set architecture (cont.) Operands: the data being operated on How are the bits interpreted? (int, FP, signed/unsigned) What size are they? (byte, word, etc.) How do we reference operands? Instruction formats: how instructions are encoded Data storage Registers Small, fast set of on-chip storage (primarily for speed) Referenced by name Memory Larger, slower set of storage (primarily for capacity) Organized as hierarchy … … but programmer references single range of addresses Memory issues Aligned data: address divisible by number of bytes Endianness: 80x86 data is little endian 7/19/2018 Microprocessors I: Lecture 11

Microprocessors I: Lecture 11 Review: x86 memory Two memory modes Real mode (DOS): only lowest 1 MB of memory Protected mode (Windows): 32-bit or 40-bit addressing Two memory models Segmented memory model Only subset of address space active Segment registers indicate start of active regions (segments) Actual address = effective address + segment base address Flat memory model Entire memory space active Actual address = effective address 7/19/2018 Microprocessors I: Lecture 11

Review: data & data transfer instructions x86 data Registers: access as 8-bit (e.g. AL, AH), 16-bit (AX), 32-bit (EAX) Memory Data size usually matches register If not, explicitly specify (BYTE PTR, WORD PTR, DWORD PTR) MOV: basic data transfer Can use registers, memory, immediates If segment reg. is destination, source must be register MOVSX/MOVZX Sign-extend or zero-extend register/memory value XCHG Exchange contents of source, dest 7/19/2018 Microprocessors I: Lecture 11

Review: data transfer, arithmetic LEA: load effective address Calculate EA/store in register Reviewed flags: CF, AF, SF, ZF, PF, OF Addition instructions ADD AX,BX  AX = AX + BX ADC AX,BX  AX = AX + BX + CF INC AX  AX = AX + 1 Subtraction instructions SUB AX,BX  AX = AX – BX SBB AX,BX  AX = AX – BX – CF DEC AX  AX = AX – 1 NEG AX  AX = -AX = 0 - AX 7/19/2018 Microprocessors I: Lecture 11

Review: Multiplication & division Multiplication instructions MUL (unsigned), IMUL (signed) Result uses 2x bits of source Source usually implied (AL/AX/EAX) Division instructions DIV (unsigned), IDIV (signed) Implied source (AX, (DX,AX), (EDX,EAX)) 2x bits of specified source Quotient/remainder split across result 7/19/2018 Microprocessors I: Lecture 11

Review: Logical instructions Logical instructions (AND/OR/XOR/NOT) Basic shift instructions Move value by <amt> bits; add 0s to left or right CF = last bit shifted out SHL <src>, <amt>: Move <src> to left SAL exactly the same SHR <src>, <amt>: Move <src> to right Arithmetic right shift Move value right by <amt> bits Copy sign bit to fill remaining bits SAR <src>, <amt> 7/19/2018 Microprocessors I: Lecture 11

Review: rotate instructions Rotate instructions: bits that are shifted out one side are shifted back in other side ROL <src>, <amt> or ROR <src>, <amt> CF = last bit rotated Rotate through carry instructions CF acts as “extra” bit that is part of value being rotated RCL <src>, <amt> or RCR <src>, <amt> 7/19/2018 Microprocessors I: Lecture 11

Microprocessors I: Lecture 11 Review: bit test/scan Bit test instructions Check state of bit and store in CF Basic test (BT) leaves bit unchanged Can also set (BTS), clear (BTR), or complement bit (BTC) Bit scan instructions Find first non-zero bit and store index in dest. Set ZF = 1 if source non-zero; ZF = 0 if source == 0 BSF: scan right to left (LSB to MSB) BSR: scan left to right (MSB to LSB) 7/19/2018 Microprocessors I: Lecture 11

Microprocessors I: Lecture 11 Review: compare CMP D, S Flags show result of (D) – (S) Condition codes: mnemonics implying certain flag conditions 7/19/2018 Microprocessors I: Lecture 11

Review: conditional instructions Conditional move Move performed only if condition is true SETcc D Sets single byte destination to 1 (01H) if condition true; all 0s (00H) if condition false Can be used to build up complex conditions 7/19/2018 Microprocessors I: Lecture 11

Microprocessors I: Lecture 11 Review: jump, loop Two general types of jump Unconditional: JMP <target> Always go to target address Conditional: Jcc <target> Go to target address if condition true Loop instructions Combines CX decrement with JNZ test May add additional required condition LOOPE/LOOPZ: loop if ((CX != 0) && (ZF == 1)) LOOPNE/LOOPNZ: loop if (CX != 0) && (ZF == 0)) 7/19/2018 Microprocessors I: Lecture 11

Microprocessors I: Lecture 11 Final notes Next time: Exam 1—PLEASE BE ON TIME!! Reminders HW 3 to be posted Final exam scheduled: Monday, 12/15, 3-6 PM 7/19/2018 Microprocessors I: Lecture 11