Berkeley Cluster: Zoom Project

Slides:



Advertisements
Similar presentations
Daniel Schall, Volker Höfner, Prof. Dr. Theo Härder TU Kaiserslautern.
Advertisements

Basic Computer Hardware and Software.
Computer Architecture & Organization
Lecture 2: Modern Trends 1. 2 Microprocessor Performance Only 7% improvement in memory performance every year! 50% improvement in microprocessor performance.
IBM RS6000/SP Overview Advanced IBM Unix computers series Multiple different configurations Available from entry level to high-end machines. POWER (1,2,3,4)
1 Network Performance Model Sender Receiver Sender Overhead Transmission time (size ÷ band- width) Time of Flight Receiver Overhead Transport Latency Total.
Slide 1 Computers for the Post-PC Era John Kubiatowicz, Kathy Yelick, and David Patterson IBM Visit.
Server Platforms Week 11- Lecture 1. Server Market $ 46,100,000,000 ($ 46.1 Billion) Gartner.
UNIT 9 Computer architecture
Virtual Network Servers. What is a Server? 1. A software application that provides a specific one or more services to other computers  Example: Apache.
V Material obtained from summer workshop in Guildford County.
Department of Computer and Information Science, School of Science, IUPUI Dale Roberts, Lecturer Computer Science, IUPUI CSCI.
Chapter 4 COB 204. What do you need to know about hardware? 
UC Berkeley 1 The Datacenter is the Computer David Patterson Director, RAD Lab January, 2007.
2007 Sept 06SYSC 2001* - Fall SYSC2001-Ch1.ppt1 Computer Architecture & Organization  Instruction set, number of bits used for data representation,
1 Recap (from Previous Lecture). 2 Computer Architecture Computer Architecture involves 3 inter- related components – Instruction set architecture (ISA):
Egle Cebelyte. Random Access Memory is simply the storage area where all software is loaded and works from; also called working memory storage.
1 Hardware and Software b Hardware the physical, tangible parts of a computerthe physical, tangible parts of a computer keyboard, monitor, wires, chips,
Testing… Testing… 1, 2, 3.x... Performance Testing of Pi on NT George Krc Mead Paper.
Computer Organization & Assembly Language © by DR. M. Amer.
EVLA Data Processing PDR Scale of processing needs Tim Cornwell, NRAO.
Academic PowerPoint Computer System – Architecture.
Basic Computer Hardware and Software. Guilford County SciVis V
Parallel IO for Cluster Computing Tran, Van Hoai.
Basic Computer Hardware and Software.
1 IRAM Vision Microprocessor & DRAM on a single chip: –on-chip memory latency 5-10X, bandwidth X –improve energy efficiency 2X-4X (no off-chip bus)
Introduction to Computers - Hardware
HTCC coffee march /03/2017 Sébastien VALAT – CERN.
William Stallings Computer Organization and Architecture 6th Edition
Chapter 6 System Integration and Performance
Basic Computer Hardware and Software.
Memory P2 Understand hardware technologies for game platforms
Lynn Choi School of Electrical Engineering
Chapter 2.
Berkeley Cluster Projects
Computer Architecture & Operations I
Hardware Technology Trends and Database Opportunities
UNIT 9 Computer architecture
Local Area Networks, 3rd Edition David A. Stamper
Basic Computer Hardware and Software.
Rough Schedule 1:30-2:15 IRAM overview 2:15-3:00 ISTORE overview break
RAM, CPUs, & BUSES Egle Cebelyte.
Basic Computer Hardware & Software
CLUSTER COMPUTING Presented By, Navaneeth.C.Mouly 1AY05IS037
Parallel Data Laboratory, Carnegie Mellon University
Architecture & Organization 1
Scaling for the Future Katherine Yelick U.C. Berkeley, EECS
IDISK Cluster 8 disks, 8 CPUs, DRAM /shelf
CS : Technology Trends August 31, 2015 Ion Stoica and Ali Ghodsi (
Computer Architecture CSCE 350
הכרת המחשב האישי PC - Personal Computer
Basic Computer Hardware and Software.
Computer Basics.
CS775: Computer Architecture
HARDWARE SPECIFICATIONS.
An Overview of the Computer System
Computers for the Post-PC Era
Lecture 2: Performance Today’s topics: Technology wrap-up
Architecture & Organization 1
Performance of computer systems
Memory P2 Understand hardware technologies for game platforms
Today’s agenda Hardware architecture and runtime system
Welcome to Architectures of Digital Systems
Computer Evolution and Performance
INTRODUCTION TO COMPUTERS
Performance of computer systems
A microprocessor into a memory chip Dave Patterson, Berkeley, 1997
IRAM Vision Microprocessor & DRAM on a single chip:
Cluster Computers.
Presentation transcript:

Berkeley Cluster: Zoom Project 3 TB storage system 370 8 GB disks, 20 200 MHz PPro PCs, 100Mbit Switched Ethernet System cost small delta (~30%) over raw disk cost Application: San Francisco Fine Arts Museum Server 70,000 art images online Zoom in 32X; try it yourself! www.Thinker.org (statue) Fine Arts Project - High-resolution pictures of over 60,000 objects of art stored on PhotoCD - Database allows users to search the images using keywords (titles, artist’s names) - Images converted to tiled format (GridPix), to ease zooming and scrolling within an image

User Decision Support Demand vs. Processor speed Database demand: 2X / 9-12 months Database-Proc. Performance Gap: “Greg’s Law” Moore’s Law is a laggard 250%/year for Greg 60%/year for Moore 7%/year for DRAM Decision support is linear in database size CPU speed 2X / 18 months “Moore’s Law”

Outline Technology: Disk, Network, Memory, Processor, Systems Description/Performance Models History/State of the Art/ Trends Limits/Innovations Technology leading to a New Database Opportunity? Common Themes across 5 Technologies Hardware & Software Alternative to Today Benchmarks

Review technology trends to help? Desktop Processor: + SPEC performance – TPC-C performance, – CPU-Memory perf. gap Embedded Processor: + Cost/Perf, + inside disk – controllers everywhere Disk Memory Network Capacity + + … Bandwidth + + + Latency – – – Interface – – –

IRAM: “Intelligent RAM” C C Proc B u s I/O I/O Microprocessor & DRAM on a single chip: on-chip memory latency 5-10X, bandwidth 50-100X serial I/O 5-10X v. buses improve energy efficiency 2X-4X (no off-chip bus) reduce number of controllers smaller board area/volume $ $ L2$ C C Bus Bus C $B for separate lines for logic and memory Single chip: either processor in DRAM or memory in logic fab D R A M I/O I/O ... Proc D R A M Bus D R A M

“Intelligent Disk”(IDISK): Scalable Decision Support? Low cost, low power processor & memory included in disk at little extra cost (e.g., Seagate optional track buffer) Scaleable processing AND communication as increase disks cross bar How does TPC-D scale with dataset size? Compare NCR 5100M 20 node system (each node is 8 133 MHz Pentium CPUs), March 28, 1997; 100 GB, 300GB, 1000GB Per 19 queries, all but 2 go up linearly with database size: (3-5 vs 300, 7-15 vs. 1000) e.g, interval time ratios 300/100 = 3.35; 1000/100=9.98; 1000/300= 2.97 How much memory for IBM SP2 node? 100 GB: 12 processors with 24 GB; 300 GB: 128 thin nodes with 32 GB total; 256 MB/node (2 boards/processor) TPC-D is business analysis vs. business operation 17 read only queries; results in queries per Gigabyte Hour Scale Factor (SF) multiplies each portion of the data: 10 to 10000 SF 10 is about 10 GB; indices + temp table increase 3X - 5X cross bar cross bar IRAM IRAM IRAM IRAM … … … … … … IRAM IRAM IRAM IRAM … … …