Session-1 Design with PLDs and FPGAs Course Name “Design with PLDs & FPGAs” Course Code: 11-EC-312 L-T-P: 3-0-2 Credits: 4

Course Context and Overview This course introduces the Circuit design engineering with programmable logic devices (PLDs) It covers Programmable Read only Memories(PROM)s, Programmable Logical Element (PLE)s Complex Programmable Logic Devices(CPLD)s, Field Programmable Gate Array(FPGA)s New generation architectures

COGNITIVE PROCESSES ASSOCIATED WITH THE COURSE S.No Cognitive Level Selected/ Not- Selected Explanation for selection and non-selection based on the nature of the course and instructor’s preferences 1. Remember Selected Fundamentals of Number systems, code conversions techniques and Boolean algebra and some mathematical formulae to be remembered 2. Understand K-maps and K-map minimization techniques should be understood to obtain the optimized digital design to perform the given function. 3 Apply Application of various flip-flops, counters and registers should be known in order to design asynchronous and synchronous sequential digital circuits. 4. Analyze The designed combinational/sequential circuits are to be analyzed to achieve the desired responses. 5. Evaluate circuits to be designed based on combinational, sequential or FSM can be evaluated to select the best choice for a particular application 5 Create New digital circuits are to be designed to achieve the desired response of the systems. The simulation tools are used to create, model the different systems to solve complex problems

Competencies At the end of the course the student will acquire these competencies (Skills) Competency POS-Levels Cognitive Level C1 Understand Full-custom & Semi Custom design methodologies to design integrated circuits. PO1-1, PO2-2, PO7-3 Understand C2 Understand the various architectures of PROM, realization of combinational & sequential logic on PLE PO1-3, PO7-2 C3 Analyze the technologies of CPLDs and FPGAs PO4-2 Apply Analyze C4 Design various combinational & sequential logic realizations On FPGA Apply C5 Implement Programmable Logic Devices with the help of new generation architectures Create, Apply

Competence 1 Competence 2 Competence 3 Competence 4 Competence 5 Title Understand Full-custom & Semi Custom design methodologies to design integrated circuits. Understand the various architectures of PROM, realization of combinational & sequential logic on PLE Analyze the technologies of CPLDs and FPGAs Design various combinational & sequential logic realizations On FPGA Implement Programmable Logic Devices with the help of new generation architectures Duration (in hours) 8 12 13 11 Session 1 Introduction to the course Introduction to PROMs Introduction-to PLD and ROM Examples of FPGA EP 300 Architecture Session 2 Introduction to IC Technology Mask Programmed ROM,PROM,EPROM,EEPROM Programmable Logic Array (PLA) Introduction to Xilinx LCA and XC3000 architecture EP 300 macrocell Session 3 Full Custom and Semi custom Design Programmable Logic Element Combinational circuit implementation using PLA XC 3000 I/O Block EP 320 architecture Session 4 Types of PLDs Combinational Logic Design using PLEs Programmable Array Logic (PAL) XC 4000 CLB architecture EP 600 architecture Session 5 Notations for PLDs Totally Self-checking Checker for Berger codes Combinational circuit implementation using PLA Programmable interconnects Session 6 1-out-of –n Detector PAL 16R8,Comparision between ROM,PLA and PAL Advanced Features of the 4000 series EP1800 Architecture Session 7 Design Methodology using PLDs, Design Software 1-out-of –90 Detector Sequential PLDs ,Complex PLDs Actel ACT Logic Module EP 1210 architecture Session 8 Assignment –Traffic light controller using ABEL Code converter for Hamming coded BCD to ASCII MAX 7000 CPLD, Xilinx XC9500 CPLD Peripheral Circuits & Routing Channels RPLD and EPLA Session 9 Multi Function Generator FPGA Architecture and Anti Fuse based FPGA Actel’s PLICE GAL 16V8 Session 10 Four bit synchronous counter design using direct feedback EPROM & SRAM based FPGA Device Capacity, Utilization and Gate Density Operation modes of OLMCs Session 11 Synchronous sequential circuit design using registered PLEs-1 Xilinx SRAM based FPGA Programming Methods 4-bit counter design Session 12 Synchronous sequential circuit design using registered PLEs-2 Comparison between FPGA, ASIC and CPLD PEEL 18CV8 Session 13 FPGA based System Design

Text Books TEXT BOOKS Parag K. Lala, “Digital System Design Programmable Logic Devices”, B S Publications 2. Debaprasad Das, “VLSI Design”, Oxford – 2011. 3. Pak K. Chan, Samiha Mourad, “Digital Design Using Field Programmable Gate Array”, Pearson Education – 2009. REFERENCE TEXT BOOKS 1.Michael John Sebasatian Smith, “Appliction Specific Integrated Circuits” Pearson Education 2.Bob Zeidman, “Designing with FPGAs and CPLDs”, CMP Books, ISBN: 1-57820-112-8. 3.Stephen Brown and Zvonko Vranesic “Fundamentals of Digital Logic with Verilog Design” Mc Graw-Hill.

Session distribution table Time Topic Conceive Design Implement Operate 05 Operation of BJT 10 Moore’s law and IC Sub-Topic-1 (Participate/Verify) Levels of Integration Sub-Topic -2 (Participate/Verify) 5 Conclusion & Summary

Questions Session – 1 Learning Plan : IC Technology At the end of this class hour on __________________my students will be able to: Define the functionality of Bipolar Junction Transistor State Moore’s law Define Integrated Circuit(IC) Define levels of integration Define SSI(Small Scale Integration) Define MSI(Medium Scale Integration) Define LSI(Large Scale Integration) Define VLSI(Very Large Scale Integration) Define feature size Illustrate levels of integration

Introduction to Digital circuits Logic gates Basic gates Universal gates Combinational circuits Half adder Full adder Sequential circuits Latches Flip flops