Very low voltage 16-bit counter in high leakage static CMOS technology

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Presentation transcript:

Very low voltage 16-bit counter in high leakage static CMOS technology Colin Stevens Low Power Electronics Elec6270 Instructor-Vishwani d. Agrawal

Theory and Simulation .18µm TSMC process in Design Architect Vth NMOS: .3725v / Vth Pmos: -.3948 |Vtp| + Vtn = .7673V 90 ns transient analysis Using ELDO Waveform Viewing in EZWAVE

Counter Selection Asynchronous Advantages Simple Design Utilizes Clock Gating Fast for small counters Disadvantages Ripple Effect Delay Grows with Counter Size Synchronous Advantages No Ripple Effect. Delay of all outputs are equal. Disadvantages More Logic Required Flip Flops are clocked even when no transition is required

Synchronous Counter

EZWAVE Vdd = 1.2V

Power, Delay, and Frequency

Log Display and Power Delay Product

% Reduction from Optimal Voltage (1.2V) Results 90ns Transient analysis Voltage Power % Reduction from Optimal Voltage (1.2V) Delay (ns) 5V 5.1264 mW -8482.62% 1.14 71.50% 4V 2.6631 mW -4358.56% 1.19 70.25% 3V 1.1481 mW -1822.15% 1.314 67.15% 2V 0.28895 mW -383.76% 1.89 52.75% 1.4V 90.81 nW -52.03% 3.18 20.50% 1.3V 74.226 nW -24.27% 3.68 8.00% 1.2V 59.73 nW 0.00% 4 1.1V 48.232 nW 19.25% 5 -25.00% 1V 39.629 nW 33.65% 7 -75.00% .9V 33.518 nW 43.88% 9 -125.00% .77V 25.699 nW 56.97% 17 -325.00% .76V 25.503 nW 57.30% 19 -375.00% Frequency 1/(delay + 10%) (Mhz) 797.45 763.94 691.85 481 285.88 247.04 227.27 181.82 129.87 101.01 53.48 47.85

Sub-threshold Results Voltage Power (nW) Delay (ns) Frequency 1/(delay + 10%) 0.6 20.60 88 10.33 Mhz 0.5 2.07 477 1.91 Mhz 0.4 0.84 3,640 0.25 Mhz 0.3 0.34 30,700 29.61 Khz 0.2 0.20 245,000 3.71 Khz 0.1 0.09 1,880,000 480 Hz

Optimizations and Conclusions Potential Optimization Low threshold gates could be used along the critical path of and gates to make the circuit faster at lower voltages. Conclusions Tradeoff between power and delay for a given circuit. I would like to have gotten the predictive models to work.

References Agrawal, V. D. (2007). Power Dissipation in CMOS Circuits [Power Point Presentation]. Retrieved from: http://www.eng.auburn.edu/users/agrawvd/COURSE/E6270_Spr09/LECTURES/lpd_4_CMOSPower.ppt Counter. (nd) .Retrieved April 15, 2009, from Wikipedia Website: http://en.wikipedia.org/wiki/Counter Low-power electronics. (nd). Retrieved April 15, 2009, from Wikipedia Website: http://en.wikipedia.org/wiki/Low-power_electronics Kulkarni, Vidya (nd). Logic Design Chapter – 5 [PowerPoint Presentation]. Retrieved from: forum.vtu.ac.in/~edusat/Prog5/logd/vrk/Chapter-5.ppt

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