NS9750 - Training Hardware.

Slides:



Advertisements
Similar presentations
IEEE 1284 I/O. IEEE 1284 Overview Four parallel port interfaces through ENI 40 pins Uses external latching transceivers Host-side only No IEEE negotiation.
Advertisements

NS Training Hardware.
Lizard Labs Peripheral Reflex System
1 ECE 263 Embedded System Design Lessons 2, 3 68HC12 Hardware Overview, Subsystems, and memory System.
NS Training Hardware. Memory Interface Support for SDRAM, asynchronous SRAM, ROM, asynchronous flash and Micron synchronous flash Support for 8,
NS Training Hardware. System Controller Module.
3-1 System peripherals & Bus Structure Memory map of the LPC2300 device is one contiguous 32-bit address range. However, the device itself is made up of.
MSP432™ MCUs Training Part 5: Digital Peripherals
Chapter 8 Input/Output. Busses l Group of electrical conductors suitable for carrying computer signals from one location to another l Each conductor in.
NetBurner MOD 5282 Network Development Kit MCF 5282 Integrated ColdFire 32 bit Microcontoller 2 DB-9 connectors for serial I/O supports: RS-232, RS-485,
SC200x Peripherals Broadband Entertainment Division DTV Source Applications July 2001.
LPC2148 Programming Using BLUEBOARD
NS Training Hardware.
Samsung ARM S3C4510B Product overview System manager
1 ARM University Program Copyright © ARM Ltd 2013 General Purpose I/O.
NS7520.
NS Training Hardware. Serial Controller - UART.
NS Training Hardware.
ATtiny23131 A SEMINAR ON AVR MICROCONTROLLER ATtiny2313.
NS Training Hardware. Print Engine Controller NS9775.
Embedded Network Interface (ENI). What is ENI? Embedded Network Interface Originally called DPO (Digital Product Option) card Printer without network.
NS Training Hardware Traffic Flow Note: Traffic direction in the 1284 is classified as either forward or reverse. The forward direction is.
Lecture 4 General-Purpose Input/Output NCHUEE 720A Lab Prof. Jichiang Tsai.
NET+OS 6.1 Training. GPIO APIs NET+OS 6.1 Signal Multiplexing System tradeoffs affecting pin count at design-time. –NS9750 unit cost reduced by conserving.
Memory Organisation & Modes of Operations By: Prof. Mahendra B. Salunke Asst. Prof., Department of Computer Engg, SITS, Pune-41
Components of a typical full-featured microcontroller.
STM32F107VC Datablad Reference manual Schematics.pdf.
The 8085A is a general-purpose microprocessor with low hardware overhead requirements. Within the 8085A are contained the functions of clock generation,
Revision questions CENG2400 v.14b 1 CENG2400 Revision, Question 1 A system has an ARM processor with a 32-bit General Purpose Input Output (GPIO) module.
نظام المحاضرات الالكترونينظام المحاضرات الالكتروني The 8085 Microprocessor Architecture.
1 The LPC1768 Architecture (with focus on Cortex-M3)
 The LPC2xxx devices currently have two on- chip UARTS.  Except UART1 has additional modem support.
8255 Programmable Peripheral Interface
Cypress Roadmap: Platform PSoC®
8051 Pin - out PORT 0 PORT 1 PORT 2 PORT 3.
Microcontrollers & GPIO
Interfacing I/O Devices
Fri. Sept 29 Announcements
NS Training Hardware.
Chapter 11: Inter-Integrated Circuit (I2C) Interface
Refer to Chapter 10 in the reference book
I/O Memory Interface Topics:
Programming Microcontroller ADC – Analog Digital Converter
contains 8086 processor and several additional functional chips: clock generator 2 independent DMA channels PIC 3 programmable 16-bit timers.
RX Compare Match Timer (CMT)
RX 8-Bit Timer (TMR) 4/20/2011 Rev. 1.00
Programming Microcontroller GPIO – General Purpose Input/Output
The Arduino Microcontroller: Atmel AVR Atmega 328
An Introduction to Microprocessor Architecture using intel 8085 as a classic processor
Subject Name: Microcontroller Subject Code: 10ES42
Computer Organization and Design
Introduction to Microprocessors and Microcontrollers
CENG2400 Revision Q1a A system has an ARM processor with a 32-bit General Purpose Input Output (GPIO) module. Two on/off switches are connected to bit-3.
SPI Protocol and DAC Interfacing
AT91 Memory Interface This training module describes the External Bus Interface (EBI), which generatesthe signals that control the access to the external.
FPro Bus Protocol and MMIO Slot Specification
NS Training Hardware.
Cypress Roadmap: CapSense® Controllers
NetSilicon & Digi Confidential
Md. Mojahidul Islam Lecturer Dept. of Computer Science & Engineering
Programmable Peripheral Interface
嵌入式微控制器编程 Embedded Microcontroller Programming
Md. Mojahidul Islam Lecturer Dept. of Computer Science & Engineering
8051 Micro Controller.
Digital Signal Processors-1
UNIT-III Pin Diagram Of 8086
Wireless Embedded Systems
NS Training Hardware.
NS Training Hardware.
Presentation transcript:

NS9750 - Training Hardware

BBus Utility Block

BBus Utility Overview Contains global BBus functions including: Master Peripheral Resets BBus DMA Interrupts ARM Wake-up USB Configuration Endian-ness Configuration General Purpose I/O (GPIO)

BBus Utility – Master Reset Master Reset Register contains reset control bits for each BBus peripheral block: Bbus Utility, BBus DMA, I2C, IEEE 1284, USB and the Serial Controllers (4) Resets asserted by default after power-on Reset bits must be de-asserted following power-on reset for each BBus peripheral.

BBus Utility – DMA Interrupts DMA Interrupt Status/Enable registers include 1-bit for each of the 16 BBus DMA Channels. Refer to the Users Manual for BBus DMA channel assignments. DMA Interrupt Status Register should be used to determine which DMA Channel is responsible for setting the BBus Bridge DMA Interrupt Pending status bit .

BBus Utility Configuration USB Configuration Register contains Speed and Host/Device mode control bits. Refer to the USB documentation in the Users Manual for further information. Endian-ness Configuration Register controls the Little/Big endian orientation of each of the BBus peripherals and the AHB Master. Endian-ness of the AHB Master must always match that of the AHB Bus.

BBus Utility – ARM Wake-up It is possible to Wake-up a sleeping ARM processor by matching pre-defined byte characters on the Serial Controller ‘A’ receive interface. Should any Rx character byte match a byte in the ARM Wake-Up Register, a wakeup signal will be forwarded from the Bbus to the System Controller Module (SCM).

BBus Utility – GPIOs 50 General Purpose I/O (GPIO) bits Each bit can be programmed to select one of the 4 Functions behind that GPIO pin. For example, GPIO[0] can be allocated to: Function 0: Ser ChanA TxData _OR_ Function 1: AHB DMA Chan0 Done _OR_ Function 2: Timer 1 _OR_ Function 3: generic GPIO bit<0>

BBus Utility – GPIOs Each GPIO Configuration Registers (#1 - #7) control 8 GPIO pins, using 4-bits to select direction and function per GPIO pin. Refer to the NS9750 DataSheet for GPIO Mux function assigments. For general purpose bits, select Function 3 and specify the pin direction.

BBus Utility – GPIOs Use GPIO Control Registers to drive the desired value onto the associated output pin. Use GPIO Status Registers to read the input value from the associated input pin. Refer to the Users Manual for GPIO bit assignments in the Configuration, Control and Status Registers.

Hints & Kinks Do all general purpose I/Os (GPIO) have the same drive strength? No. Most GPIO pins have 2 mA drive strength with the following two exceptions. LCD Clock requires 8 mA drive strengh All other LCD outputs require 4 mA drive strength.