Continue the car washer example Experimental frame

Slides:



Advertisements
Similar presentations
Network II.5 simulator ..
Advertisements

Extended DEVSML as a Model Transformation Intermediary to Make UML Diagrams Executable Jianpeng Hu Dept. of Computer Science and Engineering Shanghai Jiao.
Modeling & Simulation. System Models and Simulation Framework for Modeling and Simulation The framework defines the entities and their Relationships that.
S NAPSHOT A LGORITHM. W HAT IS A S NAPSHOT - INTUITION Given a system of processors and communication channels between them, we want each processor to.
Lecturer: Sebastian Coope Ashton Building, Room G.18 COMP 201 web-page: Lecture.
A CHAT CLIENT-SERVER MODULE IN JAVA BY MAHTAB M HUSSAIN MAYANK MOHAN ISE 582 FALL 2003 PROJECT.
Copyright © 1998 Wanda Kunkle Computer Organization 1 Chapter 2.1 Introduction.
Simulation Waiting Line. 2 Introduction Definition (informal) A model is a simplified description of an entity (an object, a system of objects) such that.
DEVS and DEVS Model Dr. Feng Gu. Cellular automata with fitness.
Graduate Program in Engineering and Technology Management
©Ian Sommerville 2004Software Engineering, 7th edition. Chapter 11 Slide 1 Architectural Design.
Analysis of Simulation Results Andy Wang CIS Computer Systems Performance Analysis.
OMNET++. Outline Introduction Overview The NED Language Simple Modules.
(C) 2009 J. M. Garrido1 Object Oriented Simulation with Java.
Develop DEVS Models Using DEVSJAVA Dr. Feng Gu. DEVS atomic model Elements of an atomic model input events output events state variables state transition.
Chapter 3 System Performance and Models. 2 Systems and Models The concept of modeling in the study of the dynamic behavior of simple system is be able.
Entities and Objects The major components in a model are entities, entity types are implemented as Java classes The active entities have a life of their.
Chapter 2 – Fundamental Simulation ConceptsSlide 1 of 46 Chapter 2 Fundamental Simulation Concepts.
ECE 449/549 Class Notes # 4 DEVS Models for Processing and Coordinating Workflow / System Entity Structure Sept
Modeling and Simulation Discrete-Event Simulation
ECE 449/549 Class Notes #1 Introduction to System Modeling Concepts and DEVS Sept
SIMULATION OF A SINGLE-SERVER QUEUEING SYSTEM
NETWORK HARDWARE CABLES NETWORK INTERFACE CARD (NIC)
Modelling DEVS applications The CD++ tool
OPERATING SYSTEMS CS 3530 Summer 2014 Systems with Multi-programming Chapter 4.
DEVS M&S Tutorial 2 Chungman Seo
Modeling with Parallel DEVS Serialization in DEVS models Select function Implicit serialization of parallel models E-DEVS: internal transition first,
Chapter 3 System Performance and Models Introduction A system is the part of the real world under study. Composed of a set of entities interacting.
Simulator Protocol. coordinator simulator Component tN tN. tL After each transition tN = t + ta(), tL = t simulator Component tN tN. tL simulator Component.
OPERATING SYSTEMS CS 3530 Summer 2014 Systems and Models Chapter 03.
Transforming DEVS to Non-Modular Form For Faster Cellular Space Simulation Arizona Center for Integrative Modeling and Simulation Electrical and Computer.
ECE 449/549 Class Notes #3 DEVS Simulators and Executors / Methodology : How to model and simulate Sept
(C) J. M. Garrido1 Objects in a Simulation Model There are several objects in a simulation model The activate objects are instances of the classes that.
COMP155 Computer Simulation September 10, Discrete Event Simulation  discrete event simulation: state variable change only at a discrete set of.
DEVS-based Modeling and Simulation References: 1.B. P. Zeigler, Hessam S. Sarjoughian, Introduction to DEVS Modeling and Simulation with JAVA: Developing.
Module 3 Distributed Multiprocessor Architectures.
ECE 449/549 Class Notes #2 Introduction to Discrete-Event Systems Specification (DEVS) Sept
Chapter 5 Concurrency: Mutual Exclusion and Synchronization Operating Systems: Internals and Design Principles, 6/E William Stallings Patricia Roy Manatee.
How Do Users Share Computer Files?
Before we start Literature review abstract DEVSJAVA license form
Continue the car washer example Experimental frame
OPERATING SYSTEMS CS 3502 Fall 2017
Parallel DEVS & DEVSJAVA
Threads vs. Events SEDA – An Event Model 5204 – Operating Systems.
Component 2 6G, H, I, J, K.
Definition of Distributed System
SOFTWARE DESIGN AND ARCHITECTURE
Getting Started .Cont The Basic Process Panel
Parallel Programming By J. H. Wang May 2, 2017.
Structural style Modular design and hierarchy Part 1
Part 3 Design What does design mean in different fields?
Introduction to Operating System (OS)
Chapter 9 Cellular Spaces
DEVS Background DEVS = Discrete Event System Specification
Suggested Project Report Outline
Atomic Model Simulator
Uniprocessor scheduling
Time Gathering Systems Secure Data Collection for IBM System i Server
Introduction to DEVSJAVA
Chapter 2: The Linux System Part 5
Performance Evaluation of Computer Networks
DEVS Background DEVS = Discrete Event System Specification
Performance Evaluation of Computer Networks
Uniprocessor scheduling
CE 221 Data Structures and Algorithms
Introducing Java.
CSE 550 Computer Network Design
Chapter 2 Operating System Overview
Chapter 3: Process Management
William Stallings Computer Organization and Architecture
Presentation transcript:

Continue the car washer example Experimental frame Outline Continue the car washer example Experimental frame Chapter 7 – simple architecture

Expectations After This Class Decide your project topic by Wednesday Know how DEVS works and what it can do Know how to build DEVS models and run simulation using DEVSJAVA Know how your project is going to be accomplished Your should be clear about the problem statement of your project You should be clear about the aim of your project You should have a picture of how you are going to implement your project

It is all about modeling Why DEVS ? It is all about modeling Software Engineering is not only about programming Software Engineering is not only about design Software Engineering is also about specification, analysis, and verification A different level specification from UML MDA (Model Driven Architecture)

An carwash example Chapter 4: exercise 1 part a -- car wash To simplify the problem, let’s first assume the car wash center only takes cars and will reject any incoming cars if it is busy Add random number to the car generator Let’s consider the truck Let’s consider the capacity of the car wash center Let’s analyze this system Add a test file – run simulation without simView

Processor with queue illustrating how to process a bag of inputs (multiple concurrent events) accumulate the inputs on port “in” into the queue public class procQ extends proc{ protected Queue q; public procQ(String name, double procTime ){ super(name,procTime); q = new Queue(); } public void deltext(double e, message x){ Continue(e); if (phaseIs("passive")){ for (int i=0; i< x.size(); i++) if (messageOnPort(x, "in", i)){ q.add(x.getValOnPort("in", i)); } holdIn("busy", procTime); job = (entity)q.first(); else if (phaseIs("busy")){ for (int i=0; i< x.size();i++) if (messageOnPort(x, "in", i)) { entity jb = x.getValOnPort("in", i); q.add(jb); class Queue is a container with FIFO discipline this makes sure the processed job is the one at the front public void deltint( ){ q.remove(); if(!q.isEmpty()){ job = (entity)q.first(); holdIn("busy", procTime); } else passivate(); remove the job at the front that was just finished SimpArc .procQ GenCol .Queue

Experimental Frame The main model of interest – carWashCenter Although a model, such as the carWashCenter, can be tested in a standalone fashion, it really does not “come to life” until it is coupled with a module capable of providing it input and observing its output. An experimental frame module is a coupled model, which when coupled to a model, generates input external events, monitor its running, and processes its outputs.

Experimental Frame (cont.) The design of an experimental frame reflects the objectives one has in experimenting a model. Thus the same model may be coupled to different experimental frame modules, which observe it under different conditions. Conversely, the same experimental frame module may be employed to experiment with different models under the same conditions. Two major components of a experimental frame are generator and transducer.

Experimental Frame for Workflow Performance Measurement SimpArc ef Output lines may diverge to indicate the occurrence of simultaneous events. When genr sends out a job identifier on port “out”, it goes at the same clock time, both to the “ariv” port of transd and port “out” of ef, hence eventually to some processor model. Input lines may converge, i.e., two or more source ports connected to the same destination port, can occur. Bags represent the collection of inputs that arrive simultaneously at a component. Instances of the classes genr and transd are coupled together to form the experimental frame, ef. The input port “in” of ef is for receiving solved jobs which are sent to the “solved” input port of transd via the external input coupling. There are two output ports: “out”, which transmits job identifiers sent to it by genr, and 'result which transmits the performance measures computed by transd. External output couplings bring about both these transmissions. There are two internal couplings: the output port “out” of genr sends job identifiers to the 'ariv port of transd the output port “out” of transd which couples to the 'stop input port of genr.

Experimental Frame in a Flat Coupled Model SimpArc gpt gpt start start generator (genr) out processor (proc) stop in out out arrived transducer (transd) out solved

Experimental Frame/Model Modularity SimpArc efp efP ef start start start out out generator (genr) processor (proc) stop in out out arrived transducer (transd) out out solved solved

ef Hierarchical Coupled Model efP start Processor With Queue (procQ) SimpArc efp efP ef start start out Processor With Queue (procQ) in out out out solved

Multiprocessor Architecture (chapter 7) Single Processor Multi-Server Pipeline Divide and Conquer Turn around time and throughput

Architecture Model proc coord Job_in Job_finished

Multiprocessor Architecture (chapter 7) SimpArc in DEVSJAVA – efp.java Single Processor – proc.java Multi-Server – multiServer.java Pipeline – pipeSimple.java Divide and Conquer – DandC3.java

Workflow Coordinator Models public class Coord extends proc{ public Coord(String name){ super(name,1); inports.add("setup"); inports.add("x"); outports.add("y"); public void initialize(){ passivate(); super.initialize();; } protected void add_procs(devs p){ //use devs for signature System.out.println("Default in Coord is being used"); }} Coord Atomic model I/O Behavior Description divide and conquer coordinator breaks incoming jobs into parts for processing and compiles the results into a final output pipeline coordinator routes incoming jobs through a series of processing states and outputs the results Multiserver coordinator routes incoming jobs for processing and collects the results for final output SimpArc divideCoord SimpArc pipeCoord divide Coord pipe Coord multi Server Coord SimpArc multiServerCoord

Workflow Architecture Models in out x y co p0 p1 p2 Architecture SimpArc DandC3 Coupled model Divide and conquer divide and conquer coordinator with processors Pipeline pipeline coordinator with processors Multiserver multiserver coordinator with processors SimpArc pipeLine SimpArc multiServer

Performance of Simple Workflow Architectures Processing Time Average Turnaround Time Maximum Throughput Simple Processor p 1/p Multiserver homogeneous p1,p2,p3 p1=p2 = p3 =p 3/thruput 1/p+1/p2+ 1/p3 3/p Pipeline p1 + p2 + p3 = p p1=p2 = p3=p/3 1/max{p1,p2,p3} Divide and Conquer p1=p2 = p3 =p/3 max{p1,p2,p3} p/3 SimpArc .proc SimpArc multiServer SimpArc pipeline SimpArc DandC3 Average turnaround time and maximum throughput as a function of processing time

Read chapter 7 Project Homework Send me your project statement by Wednesday Start to exercise DEVSJAVA and build your own models