Mini-drawers, FE-ASIC , Integrator and HV distribution for the Demonstrator Tile week upgrade session 2013 February 1st François Vazeille Mini-drawers FE-ASIC and associated electronics HV distribution (option 3) 1
Mini-drawers Final machining of the mock-ups: to fit the instrumentation needs and to take benefit from the CERN tests of the Slider (See Tile Upgrade Week 28 september 12) In particular: More contact of Slider with Girder rings. More space for readout. Definition of the envelop: 2
Definition of the envelop for the readout (drawing sent to the other labs) 3
Next works before the delivery to CERN of this first train Tests of new pipes for the cooling circuitry (not in aluminium to prevent corrosion). Making of the Patch Panel with holes only for HV connectors and cooling circuitry. Delivery to CERN by March 2013. The laboratories will have full freedom to drill other holes in the Patch Panel and even in the Drawers in order to implement their components. Comments: - The drawings were sent (late because of workshop problems !) to Bucarest for studies and the making of 2 or 3 new train of 4 mini-drawers. - Barcelona could contribute too. 4
Progress in the insertion tools Adjustable contacts Finger Basket Slider Adjustable contacts Some improvements of the Slider (See the details in the September meeting). Design of the first Basket : holes will be left for access to PMT Blocks. 5
We are making every effort to produce the Slider and the Basket Some delays due to a failure of the numerical-control machine-tool We are making every effort to produce the Slider and the Basket and test them at CERN ! 6
FE-ASIC and associated electronics Delivery in January of the first TACTIC chips (12 bit ADC) After all, the first tests will be made at Clermont-Ferrand, by connecting the support card to a test card provided by LAPP Annecy. 7
Summary Series of chips FATALIC 1, 2 and 3 Validation of the ″current conveyor concept″. Promising ″digital integrator″ for the Cesium calibration. Delivery of the first TACTIC. But more works are needed to converge to the Option # 2 with a single output. 8
Planning New tests of FATALIC3 at Clermont-Ferrand then at CERN, in particular for the digital integrator (Milestone: April). Tests at Clermont-Ferrand of TACTIC (Milestone: June). Design of 3in1 card including DAC for electronisc calibration (Milestone: October). Design of Mother Board 2 (Milestone: September). Combination of FATALIC3 and TACTIC on 3in1 card (with the help of Strasbourg) Preliminary tests at CERN in building 175 then Demonstrator tests (Milestone: October-November). Design (Milestone: December) and foundry of either a new FATALIC3 with new improvements (signal shape, peaking time) or a FATALIC4 including TACTIC and the same improvements. One Demonstrator in ATLAS: Spring 2014. 9
Space to supply 4 Demonstrators, HV Distribution option 3 Scheme (already shown): regulation outside the Drawers. New HV Bus boards (no active components) 12 channels. A 4-layer printed circuit: External layers as shielding, Internal layers to distribute the HVs. - Noise killers everywhere. Rear HV New HV regulation crate welcoming HV cards LV’s Space to supply 4 Demonstrators, but first only ¼ is made Front 10 CANBUS
Present status: rear cards, support cards, power supply and HV Bus cards. 20 m Irakli photo 11
Crate - Mechanics ready, but for the Patch Panel. - Rear and support cards: for 1 Demonstrator. - Once assembled, the DCS will be adapted from the present DCS. HV Bus cards: - Components for 4 Demonstrators 16 cards + 1 spare. - 1 card made and tested at 2 KV. Multiconductor cables (12 pairs) taken at CERN (standard specifications) - Tested at 3 KV during several weeks. - Ordering to do of the requested length for: 4 different short cables: distribution along the 4 Mini-Drawers. Long cables to connect the crate and the Tilecal modules: Tests to do in the building 175 with 20 m and 100 m. Planning Preliminary tests at Clermont-Ferrand then in the building 175, in such a way: Installation on a Demonstrator at CERN on September 2013. 12