EE 597G/CSE 578A Final Project

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Presentation transcript:

EE 597G/CSE 578A Final Project Phase Locked Loop Han-Wei Chen & Ming-Wei Liu

Outline Specification VCO PFD Charge Pump Divider Layout Post-Sim

PLL Spec Input Signal Square Wave 12.5 MHz Output Signal Sine Wave 0.3 V to 3.2 V Vdd Gnd 3.3V Locked Speed 6u sec

Voltage Control Oscillator

VCO -- Ring Oscillator

VCO – Delay Cell

VCO

VCO Layout

VCO Post-Sim

Phase Frequency Detector

PFD

PFD

Charge Pump

Charging

Discharging

Divider

Divider

Simulation Results – Schematic Level

Overall Layout

Layout

Post-Sim

END~