ECE2030 Introduction to Computer Engineering Lecture 15: Registers, Toggle Cells, Counters Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech

4-bit Register Register is the most fundamental storage, e.g. x86 ISA has 8 general purpose registers MIPS ISA has 32 general purpose registers Each 1-bit Flip-flop is a single bit register Cascade 4 of 1-bit FFs = A 4-bit Register in3 in2 in1 in0 1 1-bit D Flip Flop 1-bit D Flip Flop 1-bit D Flip Flop 1-bit D Flip Flop 2 out3 out2 out1 out0

Read/Write Control a Register Read: Retrieve data stored inside a flip-flop Write: Update with a new input data into a flip-flop Given 1 and 2 are continuous clock signals Output 1-bit D Flip Flop 1 2 In READ mode Output 1-bit D Flip Flop 1 2 Input In Write mode

Read/Write Control a Register 1-bit D Flip Flop Output R/W 1 2 Input

Another Read/Write Control of a Register Input 1-bit D Flip Flop Output 1 2 R/W Clock Gating

4-bit Register with Parallel Load Q3 1 2 D Q D3 R / W Q2 1 2 D Q D2 Q1 1 2 D Q D1 Q0 1 2 D Q D0

Logical Shift Register D Q D Q D Q D Q 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 Right Shift

Arithmetic Shift Register D Q D Q D Q D Q 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 Right Shift

Bidirectional Shift Register with Load (1-bit shown) 00: No shift 01: Shift Left 10: Shift Right 11: Load from Di 11 10 01 00 s1 s0 4-to-1 Mux D Q D Q D Q Q i+1 Q i Q i-1 1 2 1 2 1 2

Serial Transfer Shift In (SI) Shift Out (SO) D Q D Q D Q D Q Clock

Serial Shift Register SR4 Clear Shift Out (SO) (SI) D Q D Q D Q D Q Clock SR4 SI SO Clock Clear

Design a Serial Adder (yet another adder) A  A+B SI SR4 A SO A + S Clear B Ci Co Clock Ex: 0111 (A) + 0011 (B) ---------------- Clear SRs B  0111 (4 clks) B=0111 A=0000 B=1011 A=1000 B=1101 A=1100 B=0110 A=1110 B=0011 A=0111 B=0001 A=0011 B=0000 A=1001 B=0000 A=0100 B=0000 A=1010 Input SR4 B SI SO D Q Clear Clear Clock

Toggle Flip-Flop (Toggle Cell) Upon every clock, the output result is toggled D1 Q1 D2 Q2 D1 Transparent latch Transparent latch En En En D1 Q1=D2 Q2

Toggle Flip-Flop D1 Q1 D2 Q2 1 2 Enable Bit (or TE bit) Transparent latch Transparent latch 1 2 Toggle bit controls to toggle (T=1) or not to toggle (T=0)

Toggle F/F with Clear bit Output D1 Q1 D2 Q2 TE Bit Transparent latch Transparent latch Clear 1 2 Clear Toggle Enable Present Output Next Output X 1 Note that output changes every clock cycle (e.g. rising edge or falling edge)

Toggle F/F Symbol Clear TE Present Q Next Q X 1 TE Q CLR 1 2

Counters A register counts up or down per clock period Count in binary Could be preset: (with parallel loads) Types of counters Ripple counter Synchronous counter Mod-n counter Up/down counter BCD counter Gray code counter Ring counter  a 1 moves in a ring from one F/F to the next Johnson counter (or twisted ring count.)  The MSB is inversed and passed to the LSB)

2-bit Ripple Counter Count Enable TE Q TE Q CLR CLR 1 2 O0 O1 1 O0

2-bit Ripple Counter TE Q TE Q CLR CLR 1 2 1 Count Enable O0 O1 O0 1 O1

4-bit Ripple Counter TE Q TE Q TE Q TE Q CLR CLR CLR CLR 1 2 1 Enable TE Q TE Q TE Q TE Q CLR CLR CLR CLR 1 2 O0 O1 O2 O3 1 O0 O1 O2 O3

4-bit Synchronous Counter Clocks are applied to the inputs of all the F/F Count Enable TE Q TE Q TE Q TE Q CLR CLR CLR CLR 1 2 O0 O1 O2 O3 1 O0 =TE1 O1 O2 O4

Modulo-N (or Divide-by-N) Counter CLR CE O3 O2 O1 O0 1 2 4-bit Counter CLR Terminal Count (TC) MOD-10 counter (a BCD Counter) Mod-N Count from 0 to N-1 Then reset and start over

Cascaded BCD Counter Mod-10 Counter Mod-10 Counter O7 O6 O5 O4 O3 O2 Vdd CE CE 1 1 Mod-10 Counter Mod-10 Counter CLR CLR 2 2 TC TC O3 O2 O1 O0 O3 O2 O1 O0 O7 O6 O5 O4 O3 O2 O1 O0