Part III A workshop by Dr. Junaid Ahmed Zubairi VLSI DESIGN USING VHDL Part III A workshop by Dr. Junaid Ahmed Zubairi

Workshop References VHDL by Amos Zaslavsky (http://www.pet.ac.il ) Fundamentals of Digital Design by Brown and Vranesic, McGraw Hill Altera Training Modules

Synchronous Circuits Use a process to describe a flip flop VHDL signals are static so no need to assign q<= q All flip flops used by Altera have asynchronous reset Do not use asynchronous preset

Designing a Counter You can implement a counter using a process with statements as below: if clk’event and clk=‘1’ then count <= (count+1) mod LIMIT Where LIMIT is selected by you and Count is an inout port of type integer with range 0 to LIMIT-1

Gated Clock Code

Signals Translate to Hardware

With Variables….

Safer Method It is safer to use the first style without variables as variables may get converted into static storage nodes

Summary Only use asynchronous signals and clock in the sensitivity list If asynch signals are present, deal with them before the sync condition Each assignment in the sync process infers a flip flop

Bad Coding Example

Correct Coding Style

If You need the combo to be synchronized with the clock

Initialization Signals can only be initialized in the declarative part Signal enable:std_logic := ‘1’; Do not initialize the signals in the execution path of the process However, initializations may be ignored because FPGA components may have some well defined initial values Instead of initialization, use the real hardware reset or preset (NOT BOTH) and activate it in the beginning

LPM LPM is Library of Parameterized modules Using modules from LPM, you do not have to write VHDL architecture for some sub-systems For example, instead of doing an up-and-down counter in VHDL, you may reuse lpm_counter with generic map statements in the architecture body or use RAM module

LPM Resources Quartus_dir\eda\sim_lib VHDL source files are 220model.vhd and 220pack.vhd www.edif.org Quartus contains lpm.pdf file