Custom Designed Integrated Circuits Constructs for synthesis (IEEE 1076.6) Custom Designed Integrated Circuits Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

Custom Designed Integrated Circuits Construct Comments Library Supported IEEE package Supported: std_logic_1164, std_logic_unsigned, std_logic_signed, std_logic_arith Package Std TextIO Not supported Entity Architecture Signal, variable, generic Types and subtypes Supported: integer,enumeration, bit, std_logic, bit_vector, std_logic_vector, boolean. One dimensional arrays of above Records Ignored: physical types Not supported: time, real, multidim arrays Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

Custom Designed Integrated Circuits Construct Comments Alias Not Supported Signal, Variable initialization Signal and Variable initialization is not allowed Object classes Constants, signals and variables are allowed Operators Logical: (e.g. and ,or), relational (e.g. =, /=,>) concatenation (&) Arithmetic:+,-,[*, /, mod allowed but generates a lot of combinational hw] if package is used Subprograms Supported if declared in a package or in declaration part of architecture Multiple wait statements not allowed Now function not supported User defined resolution function not supported Attributes Subset is supported (e.g. ’event, ’right, ’left, ’range) Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

Custom Designed Integrated Circuits Construct Comments Sequential statements Wait, signal assignment, variable assignment, procedure call,if, case, loop, next exit, return, null Assert and after not supported Concurrent statements - Process - Concurrent signal assignment - Components - Block - Configuration Process with sensitivity list must contain all signals on the right hand side of signal assignments (sensitivity list is ignored) Supported Not supported Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

Register inference (interpreted by synthesis tool) A clocked process is defined as a process having one and only one of the following statements: wait until clk=’1’; -- rising edge wait until clk’event and clk=’1’; -- rising edge of clk wait until rising_edge(clk); if clk’event and clk=’1’ then -- clk in sensitivity list elsif clk’event and clk=’1’ then -- clk in sensitivity list wait until clk=’0’; -- falling edge wait until clk’event and clk=’0’; -- falling edge of clk wait until falling_edge(clk); if clk’event and clk=’0’ then -- clk in sensitivity list elsif clk’event and clk=’0’ then -- clk in sensitivity list Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

Signal Assignments in Clocked Processes A register is always inferred when a signal is assigned a value in a clocked process library ieee; use ieee.std_logic_1164.all; entity ff is port(clk, reset,d: in std_logic; q: out std_logic); end ff; architecture rtl of ff is begin process(clk,reset) if reset=’1’ then q<=’0’; elsif clk’event and clk=’1’ then q<=d; end if; end process; end rtl; Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

Variable Assignments in Clocked Processes Reading a variable before assigning a value to that variable means reading the old value i.e. a register is used for that variable If a variable is assigned before it is read no register is inferred process begin counter:=counter+1; -- inferred register -- Avoid variables in clocked processes Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

Asynchronous reset and set process(clk,reset,set) begin if reset=’1’ then -- asynchronous part q<=’0’; elsif set=’1’ then -- asynchronous part q<=’1’; elsif clk’event and clk=’1’ then -- synchronous part q<=d; end if; end process; Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

Synchronous reset and set process(clk) begin if clk’event and clk=’1’ then -- synchronous part if reset=’1’ then q<=’0’; elsif set=’1’ then q<=’1’; else q<=d; end if; end process; Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

Combinational logic inference The easiest way to imply combinational logic is to use concurrent signal assignments Processes are convenient to describe complex combinational logic Clocked processes can also infer combinational logic that drives the registers. Remember: All signal assignments in clocked processes will generate registers but combinational logic drives (on register inputs) the registers. cnter if clk’event and clk=‘1’ then cnter<=cnter+1; end if; + Register clk 1 Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

Latch inference and avoidance (in combinational processes) A latch is inferred for signals when they are not assigned under all conditional statements. if signal_x=‘1’ then signal_y<=‘0’; end if; ( a latch is inferred for signal_y) Latches must be avoided in synchronous designs. Latches infer feedback, cause difficulties in timing analysis (timing is ambiguous). Avoid latches by using one of the methods: Assign a default value at the beginning of a process Assign outputs for all input conditions Use else instead of elsif in the final priority branch Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

Latch inference and avoidance (in combinational processes) 1) signal_y<=‘0’; if signal_x=‘1’ then signal_y<=‘1’; end if; 2) if signal_x=‘0’ then signal_y<=‘0’; 3) else Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

Variables in Combinational Processes In a clocked process the variables must be updated before they are written. If a variable is read before it is assigned a value, then simulation mismatch will result between RTL model and synthesized model. Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

Variables in Combinational Processes entity VarError is port(A : in Bit; B : in Bit; C : in Bit_Vector(3 downto 0); Q : out Bit_Vector(1 downto 0)); end VarError; architecture VarError_a of VarError is begin Var_Proc : process (A, B, C) variable Var : Bit_Vector(1 downto 0); begin -- process Var_Proc if Var = "00" then Q <= C(1 downto 0); else Q <= C(3 downto 2); end if; var := A & B; end process Var_Proc; end VarError_a; Not OK Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

Variables in Combinational Processes entity VarOK is port(A : in Bit; B : in Bit; C : in Bit_Vector(3 downto 0); Q : out Bit_Vector(1 downto 0)); end VarOK; architecture VarOK_a of VarOK is begin Var_Proc : process (A, B, C) variable Var : Bit_Vector(1 downto 0); begin -- process Var_Proc var := A & B; if Var = "00" then Q <= C(1 downto 0); else Q <= C(3 downto 2); end if; end process Var_Proc; end VarOK_a; OK Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

Variables in Combinational Processes Synthesized result in booth cases = A,B C(3:0) Q(0) Q(1) Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

Custom Designed Integrated Circuits State machines Design rules Provide two processes, one for the state register and one for combinational logic (next state) Add a combinational process for outputs. This process can be clocked or not ( or even assignments in concurrent part) As a first choice use enumerated data type for state Safe FSM with No Lock Up Define the number of enumeration for states to be a power of two. In the case statement use when others for not used states. type state is (s0,s1,s2,s3,s4,s5,s6,s7); -- 5 states used -- case state is when s0 => when s4 => when others => Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

Common design errors Signals and variables process (a,b,c,d,int) begin int<=a and b and c; q<=int and d; end process; required process (a,b,c,d) variable int: std_logic; begin int:=a and b and c; q<=int and d; end process; Best method for intermediate storage!! Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

Common design errors Logic synthesis and sensitivity list Some synthesis tools don’t care what is in sensitivity list (all signals are assumed to be in the list)! This can lead to mismatch between simulation and synthesis! Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

Common design errors Buffers and internal dummy signals If you want to reread an output signal: Declare the signal as buffer Use an internal dummy signal Use (VHDL-93) signal attribute ‘driving_value If buffer is used it can give problems if you only want out on higher levels! top C1 out buffer Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

Common design errors Declaring vectors with downto or to signal a: std_logic_vector(0 to 3); signal b: std_logic_vector(3 downto 0); It is recommended that downto is used because index 0 will be LSB and highest index MSB. If to is used then index 0 is MSB Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

Common design errors Incomplete combinational process In combinational processes the output signals must always be assigned a value when the process is running. Otherwise latches are created (normally not wanted) Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

Custom Designed Integrated Circuits Design tips Vector multiplier It is possible to use the “*” to multiply two vectors. Note that only combinational logic is created at synthesis (many gates used). library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity v_mult is port(a,b: in std_logic_vector(3 downto 0); c: out std_logic_vector(7 downto 0)); end; architecture rtl of v_mult is begin c<=a*b; end rtl; Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

Custom Designed Integrated Circuits VHDL Modelling Guidelines (Reference: European Space Research and Technology Centre) Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

To be used in projects (and later?) General All models shall be compliant with VHDL-93 All documentation, identifiers, comments, messages, file names etc. shall use English language The code shall be consistent in writing style and naming conventions. The reserved VHDL words shall appear in uniform casing: Follow casing used in FPGA Advantage HDL Design Browser Identifiers shall be written using mixed casing The code shall emphasize good readability The code shall be properly intended. Use 3 spaces. Don’t use TAB, as TAB is environment dependent Maximum one statement per line Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

To be used in projects (and later?) Names Meaningful non-cryptic identifier names shall be used, based on the English language For signals and variables that are active low use suffix _N as in Reset_N The name shall indicate the purpose of the object and not its type e.g. AddressCounter rather than CountLoad8. Use mixed casing for names Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

To be used in projects (and later?) Comments The purpose of comments is to allow the function of a model or testbench to be understood by a designer not involved in the design of the VHDL code All models shall be fuly documented with explanatory comments in English. The comments shall be placed close to the part of the code they describe. All comments shall be intended and aligned for good readability. Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

To be used in projects (and later?) Header Each file shall contain a header with the following information Name of the design unit in the file File name Purpose of the code, description of hardware modeled Author(s) Change list, containing version numbers, authors(s), the dates and a list of all changes performed Each subprogram declaration, subprogram, process, block etc. shall be immediately preceded by a description of its function Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3

To be used in projects (and later?) Signals and ports The same name shall be used for a signal throughout all levels of the model, wherever possible. In cases where exactly the same name cannot be used e.g. when two identical sub-components have been instantiated, name derived from the same base name should be used The buffer mode shall never appear in the port of the model’s top-level entity declaration Subprograms All processes shall be associated with a descriptive label All processes with only one wait statement (e.g. typical for synthesizable processes) should use sensitivity list instead of wait statements, since this increases readability. Custom Designed Integrated Circuits ©joal 2005 HT:1 Em3