EKT 221 : Digital 2 COUNTERS

Synchronous Counter To eliminate the "ripple" effects, a common clock pulse for each flip-flop and a combinational circuit are used to generate the next state. For an up-counter (counts up by 1), an incrementer is used.

Synchronous Counter

Synchronous Counter Serial Gating

Synchronous Counter Internal Logic XOR complements each bit AND chain causes complement of a bit if all bits toward LSB from it equal 1 Count Enable Forces all outputs of AND chain to 0 to “hold” the state Carry Out Added as part of incrementer Connect to Count Enable of additional 4-bit counters to form larger counters

1 1 Present State NEXT STATE E = 1 0000 0001 0010 0011 0100 0101 0110 1 Present State NEXT STATE E = 1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

1 1 1 1 Present State NEXT STATE E = 1 0000 0001 0010 0011 0100 0101 Present State NEXT STATE E = 1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1 1

1 1 1 1 Present State NEXT STATE E = 1 0000 0001 0010 0011 0100 0101 1 Present State NEXT STATE E = 1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1 1

Binary Counter with Parallel Load Add path for input data, Di enabled for Load = 1 Add logic to : Disable count logic for Load = 1 Disable feedback from outputs for Load = 1 Enable count logic for Load = 0 & Count = 1 Load Count Action Hold Stored Value 1 Count Up Stored Value X Load D

4-bit Binary Counter with Parallel Load Clock Carry Output, CO Count Load 4-bit Binary Counter with Parallel Load Load Count Action Hold Stored Value 1 Count Up Stored Value X Load D

Converting parallel load counter into synchronous BCD counter Connect an external AND gate to LOAD Counter starts with all-zero output (0000) COUNT input always HIGH (1)

Converting parallel load counter into synchronous BCD counter AND gate = 0 (LOAD = 0), BCD counts from 0000 to 1001 Output = 1001, Q0 and Q3 in HIGH, AND gate = 1 (LOAD = 1) Next clock transition, counter load inputs (D0  D3) = 0000 following 1001 into counter. 1 1 1

Converting parallel load counter into synchronous BCD counter

Synchronous BCD Counter Y = 1, when present state = 1001 FF input equations Obtained from next – state values Simplify using K – map 1010 ~ 1111  don’t care Y = Q1Q8

Modulo – N Counter A counter that goes through a repeated sequence of N states Maximum decimal number to be counted : If Mod N = 2n then the max decimal counted is N-1 If Mod 16, then the max decimal number is 15 To determine the required number of flip- flops: n flip-flop 2n output = Mod N

Modulo – 7 Counter Use a synchronous 4 – bit binary counter with a synchronous LOAD and C LOAD – detect count “6” and load “0” Gives count of (0, 1, 2, 3, 4, 5, 6, 0, 1, …) Using don’t care for states above 0110 Detect number “6” when LOAD = Q2Q1

Modulo – 7 Counter 1 1 1

Modulo – 6 Counter : Special requirement Synchronously preset “9” on RESET and LOAD “9” on terminal count “14” Use a synchronous, 4 – bit counter with a synchronous LOAD Use LOAD signal to : preset count to “9” detect count “14” Give count of (9, 10, 11, 12, 13, 14, 9, 10, …)

Modulo – 6 Counter : Special requirement Synchronously preset “9” on RESET and LOAD “9” on terminal count “14” 1 1 1 1

Arbitrary Count Sequence Design a counter with sequence of six states as in Table 7-10

Arbitrary Count Sequence 2 states are not included : 011 and 111 Simplified equations :

Arbitrary Count Sequence Logic diagram of the arbitrary counter

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