Characterization of the APSEL4D MAPS chip Giuliana Rizzo INFN and University, Pisa on behalf of SLIM5-Collaboration & SVT-SuperB group May 2008 Elba SuperB Meeting SVT Parallel Session May 31, 2008 G. Rizzo SuperB Elba Meeting - May 31, 2008

SuperB Elba Meeting - May 31, 2008 Outline The SuperB SVT CMOS MAPS design in the APSEL chips The new pixel cell performance APSEL4D: 4k pixel matrix with sparsified redout Conclusions G. Rizzo SuperB Elba Meeting - May 31, 2008

SuperB Elba Meeting - May 31, 2008 SuperB SVT Geometry 40 cm 30 cm 20 cm Layer0 Layer Radius 0 1.5 cm 1 3.3 cm 2 4.0 cm 3 5.9 cm 4 9.1 to 12.7 cm 5 11.4 to 14.6 cm SuperB SVT concept based on Babar SVT with modifications required to operate at a L=1036 cm-2 s-1 and with the reduced SuperB boost: add a Layer0 at a very small radius to improve the resolution with high segmentation to reduce the occupancy Dt resolution (a Dz) BaBar Fast Simulation indicates target performance achievable with: b.p. inner radius: 1.0cm, Layer0 radius: 1.5 cm b.p.+Layer0 material: <0.5%-0.5% X0 Improves A beam pipe with r ~ 1 cm highly desirable, but needs to be cooled. Study is in progress to keep total thickness low ~ 0.5 % of X0 G. Rizzo SuperB Elba Meeting - May 31, 2008

SuperB Elba Meeting - May 31, 2008 Layer 0 Options The BaBar SVT technology is adequate for R > 3cm: use design similar to BaBar SVT Layer0 is subject to large backround and needs to be extremely thin: > 5MHz/cm2, 1MRad/yr, < 0.5%X0 Striplets option: mature technology, not so robust against background. Marginal with background rate higher than ~ 5 MHz/cm2 Moderate R&D needed on module interconnection/mechanics/FE chip (FSSR2) CMOS MAPS option new & challenging technology: can provide the required thickness existing devices are too slow Extensive R&D ongoing (SLIM5-Collaboration) on 3-well devices 50x50um2 Hybrid Pixel Option: tends to be too thick. An example: Alice hybrid pixel module ~ 1% X0 Possible material reduction with the latest technology improvements Viable option, although marginal G. Rizzo SuperB Elba Meeting - May 31, 2008

CMOS Monolithic Active Pixels Developed for imaging applications Several reasons make them very appealing as tracking devices : detector & readout on the same substrate wafer can be thinned down to few tens of mm radiation hardness (oxide ~nm thick) high functional density and versatility low power consumption and fabrication costs Principle of operation The undepleted epitaxial layer acts as a potential well for electrons Signal (~1000 e-) collected through diffusion by the n-well contact Charge-to-voltage conversion provided by the sensor capacitance  small collecting electrode Simple in-pixel readout (additionals nwells for PMOS not allowed in standard MAPS design!)  sequential readout PMOS “Competitive” nwells for PMOS not allowed in standard MAPS design! G. Rizzo SuperB Elba Meeting - May 31, 2008

SuperB Elba Meeting - May 31, 2008 Deep NWell MAPS design New approach in CMOS MAPS design to improve the readout speed potential: APSEL chip series SLIM5 Collaboration - INFN & Italian University Full in-pixel signal processing realized exploiting triple well CMOS process Deep nwell (DNW) as collecting electrode Gain independent of the sensor capacitance collecting electrode can be extended Area of the “competitive” nwells inside the pixel kept to a minimum:, they steel signal to the main DNW electrode. Fill factor = DNW/total n-well area ~90% in the prototype test structures Pixel structure compatible with data sparsification architecture to improve readout speed. PRE SHAPER DISC LATCH competitive nwell Deep nwell Proof of principle with the first prototypes realized in 130 nm triple well CMOS process (STMicrolectronics) G. Rizzo SuperB Elba Meeting - May 31, 2008

Submitted DNW MAPS Chips 130 nm STMicroelectronics IC group contribution: Pavia (PV)-Bergamo(BG) analog front-end Pisa(PI)-PV-BG in pixel digital logic Bologna-PI digital readout architecture Submitted DNW MAPS Chips 130 nm STMicroelectronics Sub. 8/2006 Sub. 9/2006 Sub. 12/2004 Sub. 8/2005 APSEL2M Cure thr disp. and induction APSEL2T Accessible pixel Study pix resp. APSEL2_90 TEST_STRUCT ST 130 Process characterization APSEL0 Preamplifier characteriz. APSEL1 Improved F-E 8x8 Matrix ST 90nm characterization Sub. 11/2006 Sub. 5/2007 Sub. 7/2007 Sub. 7/2007 APSEL2D APSEL2_CT APSEL3D APSEL3_T1, T2 8x32 matrix. Shielded pixel Data Driven sparsified readout Test chips to optimize pixel and FE layout Test digital RO architecture Test chips for shield, xtalk G. Rizzo SuperB Elba Meeting - May 31, 2008

SuperB Elba Meeting - May 31, 2008 APSEL generations From APSEL0 to APSEL2: proof of the DNW-MAPS principle and analog and digital readout concepts APSEL3: optimization of the pixel cell, 32x8 matrix with sparsified readout and time stamping. APSEL4: 32x128 matrix with sparsified readout and time stamping for a beam test G. Rizzo SuperB Elba Meeting - May 31, 2008

3x3 matrix, full analog output APSEL3 chips results 3x3 matrix, full analog output 90Sr electrons Landau mV S/N=23 Cluster signal (mV) Noise events properly normalized Chip 6 T1-M2 50 mm pixel pitch In the 2 versions of the front-end implemented: T1 : Noise ENC=40-52 e- <Gain> = 860 mV/fC S/N_MIP=19-23 T2: Noise ENC=27-36 e- <Gain> = 1000 mV/fC S/N_MIP=27-33 Average Signal for MIP (MPV) =980e- Sustantial redesign of the pixel cell in the APSEL3 chips with improved S/N and reduced power consumption (30 uW/ch) Major source of digital crosstalk reduced inserting a metal shield between digital lines and sensor But some digital crosstalk still present in the APSEL3 series, Under investigation. apsel2T chip 5: gain 578 mV/fC Fe55 5.9 keV calibration peak G. Rizzo SuperB Elba Meeting - May 31, 2008 Pixel signal (mV)

Periphery readout logic APSEL4D 4096 pixel matrix with data driven sparsified readout and timestamp - submitted 11/2007-received 3/2007 Pixel cell (as in APSEL3T1) & matrix implemented with full custom design and layout Sparsifying logic synthetized in std-cell from VHDL model Periphery inlcudes a “dummy matrix” (std-cell) used as digital matrix emulator Matrix subdivided in MacroPixel (MP=4x4) with point to point connection to the periphery readout logic: Register hit MP & store timestamp Enable MP readout Receive, sparsify, format data to output bus Data lines in common 2 MP private lines MP 4x4 pixels Periphery readout logic Column enable lines in common Data out bus 32x128 pixels - 50 mm pixel pitch G. Rizzo SuperB Elba Meeting - May 31, 2008

Test of the APSEL4D readout functionality With the dummy matrix implemented in the chip all the functionality of the readout have been tested. Selected dummy pixels set on and correctly readout, with the right timestamp associated, by the digital circuit. The readout is working properly even with 100% occupancy. Three clocks are used: the BCO clock, used for the timestamp counter, a faster readout clock, and a slow control clock. Test performed with RDCLK up to 50 MHz. At each rising edge of the BCO clock the readout starts to collect data from pixels fired in the previous BCO window and the first valid data are sent to the output bus after 9 RDCLK ticks. G. Rizzo SuperB Elba Meeting - May 31, 2008

SuperB Elba Meeting - May 31, 2008 Noise Scan Noise and offset of each pixel are extracted from the turn-on curve, measuring the occupancy as a function of the discriminator threshold. Logic is sensitive to 0-> 1 transitions so the occupancy (=probability to have 1 or more 0->1 transitions in a given observation time window t) is symmetric around the offset with this behavior: thr Occupancy Occu(thr) =1-P(0 hit, t,thr)=1-exp(-tn(thr)) 1 1 offset time 1 Signal at the shaper output n(thr) =noise hit rate @ thr (0->1) n0= noise hit rate @ thr=offset (0->1) s = noise Noise, offset and u0 on the free parameter extracted from a fit to the noise scan The width of the plateau region depends on tu0 @ thr = offset (average number of noise hits in the observation time). In fig.: t=1 ms, noise=5 mV different noise hit rate shown u0=1000 MHz u0=10 Occupancy u0=1 Thr (mV) G. Rizzo SuperB Elba Meeting - May 31, 2008 Offset=500mV

Example of noise scan in APSEL4D Offset Average noise and threshold dispersion at the same level ~ 9 mV  ENC = 65 e- absolute gain calibration from the Fe55 5.9 keV peak. 9 chips tested with uniform performance: Average Noise ENC = 66 e- with 25% dispersion across the matrix Average threshold dispersion 63 e- Noise Offset distribution Threshold dispersion 9 mV Noise distribution Average Noise 9 mV G. Rizzo SuperB Elba Meeting - May 31, 2008

Uniform noise and threshold dispersion Offset distribution Offset distribution Noise distribution Noise distribution G. Rizzo SuperB Elba Meeting - May 31, 2008

Absolute gain calibration from Fe55 source Fe55 Calibration Peak When the pulse height info is available gain is extracted from the position of the calibration peak 5.9 keV line (1640 e-) with charge totally collected by a single pixel PWELL NWELL P- EPI-LAYER P++ SUBSTRATE INCIDENT PHOTONS Charge entirely collected DEPLETION REGION Charge only partially collected by single pixel Fe55 5.9 keV calibration peak High thr. Pixel signal (mV) Integral rate In APSEL4D no analog information is available and the calibration peak is reconstructed from the differential rate as a function of the discriminator threshold. Can calibrate the single pixel gain …quite long procedure though! High thr. Fe55 ]peak Differential rate High thr. G. Rizzo SuperB Elba Meeting - May 31, 2008

Fe55 Calibration peak on single pixels Statistic still a bit low to distinguish the calibration peak on single pixels G. Rizzo SuperB Elba Meeting - May 31, 2008

Response of APSEL4D to Fe55 source APSEL4D - Fired pixel map with threshold around the calibration peak. Fe55 calibration peak summing up all the 4k pixels of the matrix Clearly visible the spot of the Fe55 source positioned on the bottom side of the matrix. Gain distribution from the calibration peak measured on each pixel of the matrix Average gain = 860 mV/fC with 5% dispersion (gain + thr) G. Rizzo SuperB Elba Meeting - May 31, 2008

A first look at the response to e- from Sr90 source Fired pixel map with threshold @ ½ MIP Fired pixel/event Analysis still ongoing it includes noise hits Good uniformity (the source was positioned on the left side of the matrix Clusters from Sr90 clearly visible With no momentum selection, e- from Sr90 can release a lot of energy Larger clusters and more energy released w.r.t to MIP Landau MPV ~ 130 mV, (measured with analog information on small matrix) Event with 7 pixels fired Energy>400 mV Event wuth 2 clusters 4 pixels fired Energy>230 mV G. Rizzo SuperB Elba Meeting - May 31, 2008

SuperB Elba Meeting - May 31, 2008 Digital crosstalk Although the metal shield implemented in the last pixel cell layout is effective in reducing the digital crosstalk some new effects are visible in the APSEL4D chip and are currently under investigation. By reducing the digital voltage from 1.2 to 1 V we are able to keep this effect at an acceptable level (~ 3xNoise) still being able to operate the matrix and the readout. Results shown have been obtained with the reduced digital voltage. G. Rizzo SuperB Elba Meeting - May 31, 2008

SuperB Elba Meeting - May 31, 2008 Conclusions Good progress achieved in the CMOS MAPS R&D (the most challenging option for the SVT- Layer0) Optimization of the Deep NWell MAPS pixel S/N up to 25 with power consumption reduced (~30 uW/ch) Fast redout architecture (sparsification and timestamp) implemented in the APSEL4D chip: a 4k pixel matrix. Preliminary lab tests on APSEL4D very encouraging. Threshold dispersion across matrix similar to noise ~ 65e- Good sensitivity to e- from Sr90 and to g from Fe55 source. Pixel efficiency and resolution will be measured with a testbeam in Sept. 2008 G. Rizzo SuperB Elba Meeting - May 31, 2008

SuperB Elba Meeting - May 31, 2008 backup G. Rizzo SuperB Elba Meeting - May 31, 2008

SuperB Elba Meeting - May 31, 2008 Test Beam in Sept. 2008 Test DNW MAPS on beam Measure rate capability, efficiency, resolution Test Associative Memories - based LVL1 trigger Focus on system issues for SuperB Layer 0 application Striplets with FSSR2 chip 32x128 MAPS matrix with data driven architecture beam T-1,2,3,4 :reference telescope modules DSSD 300 mm thick, 2x2 cm2 50 mm r.o. pitch (3 chip FSSR2/side) S-1,2,3 scintillator Striplets-1,2: (1.29x7.0 cm2 ) DSSD 200 mm thick (45o) 25 p-side, 50 n-side mm pitch 50 mm r.o. pitch (chip FSSR2) MAPS-1,2 : MAPS (several mm2) 50x50 mm2 (5080 mm-thick) S1 S2 S3 T-2,1 T-4,3 Striplets-1 Striplets-2 MAPS-1 MAPS-2 G. Rizzo SuperB Elba Meeting - May 31, 2008

SVT Main activities in the last year Basic CMOS MAPS R&D (most challenging option for the Layer0): Optimization of the Deep NWell MAPS pixel S/N up to 25 with power consumption reduced (~30 uW/ch) Fast redout architecture (sparsification and timestamp) implemented in a 4k pixel matrix. Preliminary test encouraging. Good sensitivity to e- from Sr90 and to g from Fe55 source 90Sr electrons Landau mV S/N=23 Cluster signal (mV) Noise events APSEL4D - Fe55 5.9 keV calibration peak APSEL4D – Sr90 test Fired pixel map with threshodl @ ½ MIP Good uniformity (the source was positioned on the left side of the matrix APSEL4D - 32x128 pixels 50 mm pixel pitch G. Rizzo SuperB Elba Meeting - May 31, 2008

SuperB Elba Meeting - May 31, 2008 Design of a pixel module with integrated cooling and low material (< 1% X0) Crucial for a low material Layer 0 design with MAPS /Hybrid Pixel options Development of support structures with cooling microchannel integrated in the Carbon Fiber/Ceramics support Testbeam preparation (Sept. 2008 @CERN). Main goals: DNW MAPS matrix resolution & efficiency Thin (200 um) striplets module with FSSR2 readout chips (baseline option in the CDR) Demostrate LV1 copability with tracker information sent to Associative Memories New DAQ system developed for data push architecture beam T-1,2,3,4 :reference telescope modules DSSD 300 mm thick, 2x2 cm2 50 mm r.o. pitch (3 chip FSSR2/side) S-1,2,3 scintillator Striplets-1,2: (1.29x7.0 cm2 ) DSSD 200 mm thick (45o) 25 p-side, 50 n-side mm pitch 50 mm r.o. pitch (chip FSSR2) MAPS-1,2 : MAPS (several mm2) 50x50 mm2 (5080 mm-thick) S1 S2 S3 T-2,1 T-4,3 Striplets-1 Striplets-2 MAPS-1 MAPS-2 G. Rizzo SuperB Elba Meeting - May 31, 2008

SuperB Elba Meeting - May 31, 2008 Man Power for SVT Italian Institutes already involved in basic R&D on MAPS (SLIM5 Collaboration ~ 13 FTE) confirmed their interest for the SuperB project: Other groups (Roma III, Perugia), already active in MAPS R&D for ILC, expressed their interest for our activities (important synergy to exploit) …but a significant amount of work is needed to turn the SVT CDR concept into a full detector design and write a Technical Design Report. There is a lot of room for groups willing to join the effort! Details in the next slide Pisa MAPS development Light Mechanics with integrated cooling Testbeam organization LV1 trigger with Associative Memories Pavia/Bergamo Front-end for MAPS & striplets Torino Mechanics Trieste Striplets (Sensor-FSSR2 hybrids-interconnections-beam telescope) Bologna DAQ for testbeam, MAPS readout architecture Milano (just joined the SVT SuperB effort) MAPS cell & module development. Light mechanics. G. Rizzo SuperB Elba Meeting - May 31, 2008

SVT Activities from CDR to TDR Although very promising the MAPS technology might need more time to become mature for application in SuperB. On the timescale of the TDR the situation will be clearer… For the TDR we need to have a Layer0 design based on Hybrid Pixels: a mature and viable option that anyway requires some R&D to reduce the pitch and material budget to reach the SuperB requirements. Activities already started (could benefit from more manpower): Background studies to optimize detector space-time granularity and verify radiation levels (PI) Physics studies to optimize Layer0 and overall detector geometry and granularity(PI) Strong ongoing R&D on technology development for the most challenging Layer 0 option: CMOS MAPS pixel. (BO,PI,PV,BG,TO,TS, + MI ...) Activities not yet covered that need to start soon: Hybrid Pixel Option: need to investigate possible material/pitch reduction w.r.t.LHC experiments Data transmission and DAQ Design of the Layers 1-5: investigate existing front-end chip, module design Integration Issues G. Rizzo SuperB Elba Meeting - May 31, 2008

SuperB Elba Meeting - May 31, 2008 CMOS MAPS R&D goals TDR time scale: build a prototype multichip MAPS module suitable for application in Layer 0. Demonstrate the ability to build a working detector with this technology. Present R&D on DNW MAPS very encouraging Need to demonstrate fast readout architecture implementation is possible with this technology (R=5MHz/cm2, continous beam structure) Crosstalk due to digital line crossing the pixel seems cured but still some effects are present (power distribution? ) Scalability of the readout architecture to large matrix (Area ~1 cm2) 256 pixel matrix produced: test started. - 4k pixel matrix in production Nov. ’07 Issues for larger matrix: power distribution, output rate. efficiency of the readout Explore alternative architecture: data driven vs triggered architecture. Pixel cell optimization to improve S/N, charge collection efficiency, power dissipation. S/N = 1524, Power=30 mW/ch in chips just received Evaluate different technology (IBM 130 nm triple well) Radiation tolerance: tests performed on CMOS MAPS from other groups indicate adequate rad. hardness for SuperB. Some effects are design/process dependent needs to be investigated on our DNW MAPS. Irradiation program just started Optimize pixel cell for radiation hardness G. Rizzo SuperB Elba Meeting - May 31, 2008

SuperB Elba Meeting - May 31, 2008 Apsel3T1 Charge sensitivity~ 1V/fC ENC: 45e- rms (200ns) 40e- rms (400ns) Threshold dispersion: 45e- (200ns) 55e- (400ns) (from schematic simulations) In-pixel logic Satellite Nwells Sensor size: A~670m2 CD~310fF Sensor core dimensions (NW+DNW): A~360m2 P~80m Satellites dimensions (NW): A~310m2 P~180m Sensor core G. Rizzo SuperB Elba Meeting - May 31, 2008

SuperB Elba Meeting - May 31, 2008 Apsel3T2 Sensor size: A~ 680m2 CD~ 200fF Sensor core dimensions (NW+DNW): A~ 340m2 P~ 80m Satellite dimensions (NW): P~ 190m Sensor core, analog NMOS Analog and digital PMOS Layout with shields In-pixel digital logic satellites G. Rizzo SuperB Elba Meeting - May 31, 2008

MAPS Radiation Hardness Expected Background @ Layer0: Dose = 6Mrad/yr Equivalent fluence = 6x1012 neq/cm2/yr x5 safety factor included CMOS redout electronics (deep submicron) rad hard MAPS sensor - Radiation damage affects S/N Non-ionizing radiation: bulk damage cause charge collection reduction, due to lower minority carrier lifetime (trapping)  fluences ~ 1012 neq/cm2 affordable, 1013 neq/cm2 possible Ionizing radiation: noise increase, due to higher diode leakage current (surface damage)  OK up to 20 Mrad with low integration time (10 ms) or T operation < 0o C, or modified pixel design to improve it Results from standard nwell MAPS prototypes Irradiation test performed on several MAPS prototypes, with standard nwell sensor, indicate application for SuperB is viable. APSEL chips irradiation started …. G. Rizzo SuperB Elba Meeting - May 31, 2008

SLIM5-Silicon detectors with Low Interactions with Material Basic R&D for Layer0 (CMOS MAPS and thin strips) started in 2004 within the SLIM5 Collaboration. Several Italian Institutions involved in the project: BO, PI (coordination), PV-BG, TO, TN, TS. R&D project supported by the INFN and the Italian Ministry for Education, University and Research. SLIM5 Purpose: develop technology for thin silicon tracker systems (sensor/ readout/ support structure/ cooling) crucial to reduce multiple scattering effects for future collider experiments (SuperB, ILC) Realize a demonstration thin silicon tracker with LVL1 trigger capabilities: CMOS monolithic active pixels Thin strip detectors on high resistivity silicon Associative memory system for track trigger Low mass mechanical support and services Test beam foreseen in 2008 to measure rate capability, efficiency,resolution SLIM5 Project G. Rizzo SuperB Elba Meeting - May 31, 2008

SLIM5-Silicon detectors with Low Interactions with Material G. Batignani1,2, S. Bettarini1,2, F. Bosi1,2, G. Calderini1,2, R. Cenci1,2, M. Dell’Orso1,2, F. Forti1,2, P.Giannetti1,2 , M. A. Giorgi1,2, A. Lusiani2,3, G. Marchiori1,2, F. Morsani2, N. Neri2, E. Paoloni1,2, G. Rizzo1,2 , J. Walsh2 C. Andreoli4,5, E. Pozzati4,5,L. Ratti4,5, V. Speziali4,5, M. Manghisoni5,6, V. Re5,6, G. Traversi5,6, L.Gaioni4,5 L. Bosisio7, G. Giacomini7, L. Lanceri7, I. Rachevskaia7, L. Vitale7, M. Bruschi8, B. Giacobbe8,A. Gabrielli8, N. Semprini8, R. Spighi8, M. Villa8, A. Zoccoli8, D. Gamba9, G. Giraudo9, P. Mereu9, G.F. Dalla Betta10 , G. Soncini10 , G. Fontana10 , L. Pancheri10 , G. Verzellesi11 1Università degli Studi di Pisa, 2INFN Pisa, 3Scuola Normale Superiore di Pisa, 4Università degli Studi di Pavia, 5INFN Pavia, 6Università degli Studi di Bergamo, 7INFN Trieste and Università degli Studi di Trieste 8INFN Bologna and Università degli Studi di Bologna 9INFN Torino and Università degli Studi di Torino 10Università degli Studi di Trento and INFN Padova 11Università degli Studi di Modena e Reggio Emilia and INFN Padova G. Rizzo SuperB Elba Meeting - May 31, 2008

SuperB Elba Meeting - May 31, 2008 Layer0 thickness Striplets module average thickness 0.46% X0 Silicon detector 200 mm Support structure ~ 100 mm Si eq. ~3 Upilex/Cu flex layers/module ~ 135 mm Si eq. Flex multilayer with Al could reduce by ~ 3 this contribution MAPS module average thickness 0.5% X0 Double layer MAPS 100 mm Support structure (AlN) + cooling ~ 300 mm Si eq. 2 Upilex/Cu flex layers/module ~ 90 mm Si eq. ALICE hybrid pixel average thickness 1 % X0 0.37 % X0 Si sensor+readout 0.1 % X0 support 0.3 % X0 cooling 0.17 % X0 Al multilayer bus G. Rizzo SuperB Elba Meeting - May 31, 2008

Radius, thickness, resolution Technological solutions depend critically on L0 radius, thickness, resolution Fast simulation studies for various decays have been performed A full, more detailed reassessment is needed for the TDR. MAPS low mass solution would leave more flexibility for radius (ie background) and resolution Hybrid pixels will force to use the smallest radius and/or better resolution Striplets (same MAPS material) require larger radius, performance marginal Dt resolution in Bpp decays vs L0 X0(%) 10mm resolution 5mm resolution BaBar beam pipe material: 0.4% X0 b. p. inner R 1cm, o.r. 1.1 cm layer0 radii = 1.2, 1.5, 1.7 cm material for L0 = [0.2-1.5] % X0 hit resolution = [5-15] mm MAPS MAPS G. Rizzo SuperB Elba Meeting - May 31, 2008

Fast Readout Architecture for MAPS Data-driven readout architecture with sparsification and timestamp information under development. In the active sensor area we need to minimize: the logical blocks with PMOS to minimize the competitive nwell area and preserve the collection efficiency of the DNW sensor. digital lines for point to point connections to allow scalability of the architecture with matrix dimensions and to reduce cross talk with the sensor underneath. MP 4x4 pixels Matrix subdivided in MacroPixel (MP=4x4) with point to point connection to the periphery readout logic: Register hit MP & store timestamp Enable MP readout Receive, sparsify, format data to output bus Data lines in common 2 MP private lines Column enable lines in common Periphery readout logic APSEL3D: 256 pixels APSEL4D: 4k pixels Sub. Nov. 2007 Data out bus G. Rizzo SuperB Elba Meeting - May 31, 2008 50x50 um pitch

3x3 matrix, full analog output APSEL2 chips results 3x3 matrix, full analog output 90Sr electrons Landau mV S/N=14 Cluster signal (mV) 50 mm pixel pitch Cluster Multiplicity 1 2 Noise events properly normalized Hit pixels in 3x3 matrix apsel2T chip 5: gain 578 mV/fC Noise ENC = 50 e- Indications of small cluster size (1-2 pixels) Cluster Signal for MIP (Landau MPV) 700 e- S/N = 14 Threshold dispersion = 100 e- (Noise x2 still high!) Digital crosstalk effects present Cluster seed G. Rizzo SuperB Elba Meeting - May 31, 2008

Analog routing (local) Digital routing (local/global) From APSEL2 to APSEL3 APSEL2 issues APSEL3D Digital lines shielding Cross talk between digital lines and substrate Requires aF level parasitic extraction to be modeled Relatively small S/N ratio (about 15) Especially important if pixel eff. not 100% Power dissipation 60 mW/pixel Creates significant system issues M1 M2 M3 M5 M6 M4 Analog routing (local) Digital routing (local/global) Shield (VDD/GND) APSEL3 Redesigned front-end/sensor Optimize FE Noise/Power: Reduce sensor capacitance (from 500 fF to ~300 fF) keeping the same collecting electrode area reduce DNW sensor/analog FE area (DNW large C) Add standard NWELL area (lower C) to collecting electrode. New design of the analog part Optimize sensor geometry for charge collection efficiency using fast simulation developed: Locate low efficiency region inside pixel cell Add ad hoc “satellite” collecting electrodes APSEL3 Power=30 mW/pixel: Performance APSEL3 expected performance Expand this slide? Simulation Result on shiled FE Version Geom. ENC (PLS) e(@5s) S/N APSEL2 data A 50 e- 88.7% 14 APSEL3 Transc. B 41 e- 93.6% 99.4% 16 18 Curr. Mirror 31 e- 98.6% 99.9% 22 24 G. Rizzo SuperB Elba Meeting - May 31, 2008

The cure for the crosstalk (APSEL2_CT) sensor Dedicated test structures for crosstalk study on sensor with/without metal shield just received. First tests indicate shield is effective! Induced signal by digital transition (1.2V) reduced in pixel with the metal shield w.r.t no shielded version. Digital lines shield with shield 10 mV/div no shield 1 us/div No shield Residual crosstalk in shielded pixels below the level of the pixel noise (50 e- ~ 5mV) Still to investigate origin of the positive lobe…though seems not related to the digital signal on the line crossing the pixel Logic to connect digital signal to lines crossing the pixel G. Rizzo SuperB Elba Meeting - May 31, 2008

Mechanics & Module design R&D MAPS module proposed (AlN support + minichannel with cold liquid) Two MAPS layers (up/down) placed on the mechanical support forming a ladder. Each chip: 12.8mm x 12.8mm. Total Layer0 thickness: 0.5 % X0 0.1 % (Si) + 0.3 % (Supp+Cooling) + 0.1 % (bus/Cu) MAPS power dissipation is large (in the active area!) Power = 50 μW/cell = 2 W/cm2 Power dissipation drives the mechanical problem FEA for MAPS module proposed indicates power evacuation possible with a support/cooling thickness ~ 0.3% X0: Extensive R&D activity on microcooling See F. Bosi’s talk at the SVT parallel session. Need to demonstrate feasibilty with meas. on mechanical prototype Thermoidraulic Testbench in prep. for accurate thermic measurements Mechanincal activity also to optimize the design of the striplets option. G. Rizzo SuperB Elba Meeting - May 31, 2008

Why hybrid-pixel-like MAPS Modern VLSI CMOS processes (130 nm and below) could be exploited to increase the functionality in the elementary cell  sparsified readout of the pixel matrix. Data sparsification could be an important asset at future particle physics experiments (ILC, Super B-Factory) where detectors will have to manage a large data flow A readout architecture with data sparsification will be a new feature which could give some advantages with respect to existing MAPS implementations  flexibility in dealing with possible luminosity and background changes during the experiment lifespan, decouple modularity from readout speed An ambitious goal is to design a monolithic pixel sensor with similar readout functionalities as in hybrid pixels (sparsification, time stamping) G. Rizzo SuperB Elba Meeting - May 31, 2008

Deep N-Well (DNW) sensor concept New approach in CMOS MAPS design compatible with data sparsification architecture to improve the readout speed potential PREAMPL SHAPER DISC LATCH SLIM5 Collaboration - INFN & Italian University Classical optimum signal processing chain for capacitive detector can be implemented at pixel level: Charge-to-Voltage conversion done by the charge preamplifier The collecting electrode (Deep N-Well) can be extended to obtain higher single pixel collected charge (the gain does NOT depend on the sensor capacitance), reducing charge loss to competitive N-wells where PMOSFETs are located Fill factor = DNW/total n-well area ~90% in the prototype test structures G. Rizzo SuperB Elba Meeting - May 31, 2008

SuperB Vertex Detector Design Issues SuperB SVT concept based on Babar SVT with modifications required to operate at a L=1036 cm-2 s-1 and with the reduced SuperB boost Main Issues Impact on Vertex Separation significance Smaller beam energy asymmetry 7+4 GeV  bg=0.28 SuperB (bg=0.55 BaBar) Reduces average vertex separation by ~ 2 w.r.t. BaBar: <Dz>~ (bg)Y(4S) ct ~130 mm @ SuperB Time dependent analyses require <Dz>/s(Dz) > ~2 (keep BaBar as target): Radius of beam pipe and first SVT layer need to be reduced: Vertex resolution dominated by first layers: the closer to the IP the better Improves BaBar SuperB boost > Detector segmentation to reduce occupancy to acceptable level (<10%) > Radiation hardness Dose ~ 1 Mrad/yr Equivalent fluence ~ 1012 n/cm2/yr Machine backgrounds with high luminosity/ “squeezed” bunches/low currents: Present etimate (simulation) of total background rate at SVT inner layer location ~ 5 MHz/cm2 G. Rizzo SuperB Elba Meeting - May 31, 2008

SuperB Elba Meeting - May 31, 2008 Beam pipe Beampipe X0 Gold foil 4 mm 0.121 % Berillium 600 mm 0.170 % Water 300 mm 0.083 % Ni coating 7 mm 0.050 % 1.0 cm inner radius Be inner wall ≈ 4um inside Au coating 8 water cooled channels (0.3mm thick) Power ≈ 1kW Peek outer wall Outer radius ≈ 1.2cm Thermal simulation shows max T ≈ 55°C Issues Connection to rest of b.p. Be corrosion Outer wall may be required to be thermally conductive to cool pixels Total 0.42 % backup G. Rizzo SuperB Elba Meeting - May 31, 2008

An example of sensor optimization With old sensor geometry (left) Efficiency ~ 93.5% from simulation (pixel threshold @ 250 e- = 5xNoise) Inefficient regions shown with dots (pixel signal < 250 e-) Cell optimized with satellite nwells (right) Efficiency ~ 99.5% 3x3 MATRIX sensor optimized 3x3 MATRIX old sensor geom Satellite nwells connected to central DNW elect Competitive Nwells To be updated with new numbers on efficiency and plot apsel3T DNW collecting electrode G. Rizzo SuperB Elba Meeting - May 31, 2008