ISIS Synchrotron RF – Recent Work Craig Clark Krish Chelliah Dave Gibbs

TH558 HPD

June 17 - initial tests up to full gapvolts (~7kV) into 2RF6 cavity using only 1kW Int. Amp Total Cavity Impedance lower? Run without liquid resistors? TH558 HPD – initial tests

Cavity RF generation and Phase distribution Var. 90 Master Oscillator Static offset / antiphase Modulator Cavity Lock Phase Mod  Trim 1 RF. Cav.  Ref. Cavity lock Phase Mod  Phase Mod 6 x 1RF System 4 x 2RF System  modulator  Det. 2 RF. FLG Bdot Frequency Doubler BLL Rad L BPL F trim  Det. Total Accel Volts sum. Soon! Ooperationally running in FPGA since February 2016 Digital LPRF

System Timing, Freq. Increment & FF Beam Compensation broadcast over trigger lines RT – OS Controller Diagnostic virtual “scope traces” sent from FPGAs to RTOS controller via 4-Lane PCIe / Switch Fabric Backplane Digital LPRF

Windows PC control VI RF setup parameters- phase offsets, Loop gains etc (set by RF team)

Frequency Law Generator / Master Oscillator Implemented using LabView FPGA on NI PXIe7966R FPGA module + NI 5734 120MS/s digitiser adapter module generates the RF sweep from 1.3MHz to 3.1MHz for 1RF caivites and 2.6 to 6.3MHz for 2nd Harmonic cavities.

Windows PC diagnostics VI (Virtual scope traces) Enables selection and display of test signals and Displays. Currently available for a limited selection of virtual test points in the FPGA code eg radial loop input (shown above). Deployed on the Windows PC in the LabView development environment, with refresh rates available up to 20Hz or so, but will be rolled out as an executable.

R&K 3kW Intermediate Amp

Digital LPRF – Beam Phase loop (Analogue BPL on time 900dP) Dig MO with 0clks = 0us pipeline delay Dig MO with 900clks = 3.6us pipeline delay (Digital BPL on time 1200dP) Dig MO with 0clks = 0us pipeline delay Dig MO with 1153clks = 4.6us pipeline delay Digital LPRF – Beam Phase loop

Beam Compensation Unit RF – Feed forward Beam Compensation Bunch 1 Bunch 2 Tetrode Amplifiers Intermediate Amplifier Subtracter - Variable gain delay LP Filter RF demand 100Hz Compensator Function Generator Sum Electrode Level Control Servo / Cavity phase loop Beam Compensation Unit Fixed frequency – only usable over first 3ms or so

IQ FFBC on 2RF systems

Accelerating Gap Voltage envelope FF Gain Cavlock LC Servo Anode Current PtP Bunch height Tuning PD Grid-Gap Tuning PD LC Out - Gap FF I Signal No FFBC With FFBC Accelerating Gap Voltage envelope IQ FFBC on 2RF systems

Other recent / continuing work HPD Grid - Rob Bias Reg - Derek / Neil / Rob I/Ls - Neil Grid switching - Neil